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參數(shù)資料
| 型號： | CY7C374I-66AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | UltraLogic 128-Macrocell Flash CPLD |
| 中文描述： | FLASH PLD, 20 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 274K |
| 代理商： | CY7C374I-66AC |
UltraLogic 128-Macrocell Flash CPLD
fax id: 6139
CY7C374i
Cypress Semiconductor Corporation
3901 North First Street
San Jose
October 1995 – Revised December 19, 1997
CA 95134
408-943-2600
Features
128 macrocells in eight logic blocks
64 I/O pins
5 dedicated inputs including 4 clock pins
In-System Reprogrammable (ISR) Flash technology
—JTAG interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
—f
MAX
= 125 MHz
—t
PD
= 10 ns
—t
S
= 5.5 ns
—t
CO
= 6.5 ns
Fully PCI compliant
3.3V or 5.0V I/O operation
Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
TQFP packages
Pin compatible with the CY7C373i
Functional Description
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C374i is de-
signed to bring the ease of use as well as PCI Local Bus Spec-
ification support and high performance of the 22V10 to
high-density CPLDs.
Like all of the UltraLogic F
LASH
370i devices, the CY7C374i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally, be-
cause of the superior routability of the F
LASH
370i devices, ISR
often allows users to change existing logic designs while si-
multaneously fixing pinout assignments.
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
Logic Block Diagram
7C374i-1
PIM
INPUT
MACROCELL
CLOCK
INPUTS
INPUTS
4
4
36
16
16
36
LOGIC
BLOCK
A
36
16
16
36
8 I/Os
36
36
36
16
16
36
16
16
32
32
4
1
INPUT/CLOCK
MACROCELLS
I/O
0
–I/O
7
LOGIC
BLOCK
C
LOGIC
BLOCK
B
LOGIC
BLOCK
D
LOGIC
BLOCK
H
LOGIC
BLOCK
G
LOGIC
BLOCK
F
LOGIC
BLOCK
E
I/O
8
–I/O
15
I/O
16
–I/O
23
I/O
24
–I/O
31
I/O
56
–I/O
63
I/O
48
–I/O
55
I/O
40
–I/O
47
I/O
32
–I/O
39
8 I/Os
8 I/Os
8 I/Os
8 I/Os
8 I/Os
8 I/Os
8 I/Os
Selection Guide
7C374i–125
7C374i–100
7C374i–83
7C374i–66
7C374iL–66
Maximum Propagation Delay
[1]
, t
PD
(ns)
Minimum Set-Up, t
S
(ns)
Maximum Clock to Output
[1]
, t
CO
(ns)
Typical Supply Current, I
CC
(mA)
Note:
1.
The 3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V.
10
12
15
20
20
5.5
6
8
10
10
6.5
7
8
10
10
125
125
125
125
75
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C374I-66AI | UltraLogic 128-Macrocell Flash CPLD |
| CY7C374I-66GMB | UltraLogic 128-Macrocell Flash CPLD |
| CY7C374I-83AC | UltraLogic 128-Macrocell Flash CPLD |
| CY7C374I-83AI | UltraLogic 128-Macrocell Flash CPLD |
| CY7C374I-83GMB | UltraLogic 128-Macrocell Flash CPLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C374I83AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C374I-83AC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 3.2K Gates 128 Macro Cells 5V 100-Pin TQFP |
| CY7C374I-83JC | 制造商:Cypress Semiconductor 功能描述:CPLD FLASH370i Family 3.2K Gates 128 Macro Cells CMOS Technology 5V 84-Pin PLCC |
| CY7C374U66JC | 制造商:CYPRESS 功能描述:New |
| CY7C3751-66UMB | 制造商: 功能描述: 制造商:undefined 功能描述: |
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