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參數(shù)資料
| 型號： | CY7C343B |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64-Macrocell MAX EPLD(64-宏單元 MAX EPLD) |
| 中文描述： | 64宏單元最大可編程邏輯器件（64 -宏單元最大可編程邏輯器件） |
| 文件頁數(shù)： | 5/11頁 |
| 文件大小： | 161K |
| 代理商： | CY7C343B |
CY7C343B
5
Figure 1. CY7C343B Internal Timing Model
External Synchronous Switching Characteristics
Over Operating Range
Parameter
Description
7C343B-25
Min.
7C343B-30
Min.
7C343B-35
Min.
Unit
Max.
Max.
Max.
t
PD1
Dedicated Input to Combinatorial Output
Delay
[3]
I/O Input to Combinatorial Output Delay
[3]
Com
’
l/Ind
25
30
35
ns
t
PD2
t
SU
t
CO1
Com
’
l/Ind
40
45
55
ns
Global clock setup time
Com
’
l/ Ind
15
20
25
ns
Synchronous Clock Input to Output
Delay
[3]
Com
’
l/Ind
14
16
20
ns
t
H
Input Hold Time from Synchronous Clock
Input
Com
’
l/Ind
0
0
0
ns
t
WH
t
WL
f
MAX
Synchronous Clock Input HIGH Time
Com
’
l/Ind
8
10
12.5
ns
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency
[4]
Com
’
l/Ind
8
10
12.5
ns
Com
’
l/Ind
62.5
50
40
MH
z
t
CNT
t
ODH
f
CNT
Minimum Global Clock Period
Com
’
l/Ind
20
25
30
ns
Output Data Hold Time After Clock
Com
’
l/Ind
2
2
2
ns
Maximum Internal Global Clock
Frequency
[5]
Com
’
l/Ind
50
40
33.3
MH
z
Notes:
3.
4.
5.
C1 = 35 pF.
The f
values represent the highest frequency for pipeline data.
This parameter is measured with a 16-bit counter programmed into each LAB.
LOGIC ARRAY
CONTROL DELAY
t
LAC
EXPANDER
DELAY
t
EXP
CLOCK
DELAY
t
IC
t
RD
t
COMB
t
LATCH
INPUT
DELAY
t
IN
PIA
DELAY
t
PIA
REGISTER
OUTPUT
DELAY
t
OD
t
XZ
t
ZX
LOGIC ARRAY
DELAY
t
LAD
FEEDBACK
DELAY
t
FD
I/O DELAY
t
IO
INPUT/
OUTPUT
INPUT
C343B-9
SYSTEM CLOCK DELAY t
ICS
t
RH
t
RSU
t
PRE
t
CLR
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PDF描述 |
|---|---|
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| CY7C371L-66AI | UltraLogic 32-Macrocell Flash CPLD |
| CY7C371L-66JC | UltraLogic 32-Macrocell Flash CPLD |
| CY7C371L-66JI | UltraLogic 32-Macrocell Flash CPLD |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C343B-25HC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX 制造商:QP Semiconductor 功能描述:CYP 7C343B DIE |
| CY7C343B-25JC | 制造商:QP Semiconductor 功能描述:ELPRESS 7C343B DIE 25NS-PLCC |
| CY7C343B-30JC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 1.25K Gates 64 Macro Cells 40MHz 0.65um Technology 5V 44-Pin PLCC |
| CY7C343B-35JI | 制造商:QP Semiconductor 功能描述: |
| CY7C344-15JC | 制造商:Cypress Semiconductor 功能描述: |
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