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參數(shù)資料
| 型號： | CY7C343B |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64-Macrocell MAX EPLD(64-宏單元 MAX EPLD) |
| 中文描述： | 64宏單元最大可編程邏輯器件（64 -宏單元最大可編程邏輯器件） |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 161K |
| 代理商： | CY7C343B |
CY7C343B
4
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves intercon-
nect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed delay,
regardless of programmable interconnect array configuration,
simplifies design by ensuring that internal signal skews or rac-
es are avoided. The result is simpler design implementation,
often in a single pass, without the multiple internal logic place-
ment and routing iterations required for a programmable gate
array to achieve design timing objectives.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under
“
Absolute Maximum Ratings
”
may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tions of this data sheet is not implied. Exposure to absolute
maximum ratings conditions for extended periods of time may
affect device reliability. The CY7C343B contains circuitry to
protect device pins from high static voltages or electric fields;
however, normal precautions should be taken to avoid apply-
ing any voltage higher than maximum rated voltages.
For proper operation, input and output pins must be con-
strained to the range GND < (V
IN
or V
OUT
) < V
CC
. Unused
inputs must always be tied to an appropriate logic level (either
V
CC
or GND). Each set of V
CC
and GND pins must be connect-
ed together directly at the device. Power supply decoupling
capacitors of at least 0.2
μ
F must be connected between V
CC
and GND. For the most effective decoupling, each V
CC
pin
should be separately decoupled to GND, directly at the device.
Decoupling capacitors should have good frequency response,
such as monolithic ceramic types.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum ex-
pander delay t
EXP
to the overall delay. Similarly, there is an
additional t
PIA
delay for an input from an I/O pin when com-
pared to a signal from a straight input pin.
When calculating synchronous frequencies, use t
S1
if all inputs
are on the input pins. When expander logic is used in the data
path, add the appropriate maximum expander delay, t
EXP
to
t
S1
. Determine which of 1/(t
WH
+ t
WL
), 1/t
CO1
, or 1/(t
EXP
+ t
S1
)
is the lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the synchronous configura-
tion.
Typical I
CC
vs. f
MAX
Output Drive Current
When calculating external asynchronous frequencies, use
t
AS1
if all inputs are on dedicated input pins.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
AS1
. Determine which
of 1/(t
AWH
+ t
AWL
), 1/t
ACO1
, or 1/(t
EXP
+ t
AS1
) is the lowest
frequency. The lowest of these frequencies is the maximum
data path frequency for the asynchronous configuration.
The parameter t
OH
indicates the system compatibility of this
device when driving other synchronous logic with positive in-
put hold times, which is controlled by the same synchronous
clock. If t
OH
is greater than the minimum required input hold
time of the subsequent synchronous logic, then the devices
are guaranteed to function properly with a common synchro-
nous clock under worst-case environmental and supply volt-
age conditions.
200
150
100
50
1 kHz
10 kHz
100 kHz
1 MHz
I
C
MAXIMUM FREQUENCY
10 MHz
50 MHz
0
A
V
CC
= 5.0V
Room Temp.
C343B
–
7
0
1
2
3
4
I
O
V
O
OUTPUTVOLTAGE (V)
250
200
150
100
50
5
I
OH
I
OL
V
CC
= 5.0V
Room Temp.
C343B
–
8
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C343B-25HC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX 制造商:QP Semiconductor 功能描述:CYP 7C343B DIE |
| CY7C343B-25JC | 制造商:QP Semiconductor 功能描述:ELPRESS 7C343B DIE 25NS-PLCC |
| CY7C343B-30JC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 1.25K Gates 64 Macro Cells 40MHz 0.65um Technology 5V 44-Pin PLCC |
| CY7C343B-35JI | 制造商:QP Semiconductor 功能描述: |
| CY7C344-15JC | 制造商:Cypress Semiconductor 功能描述: |
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