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參數(shù)資料
| 型號： | CY7C341 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 192-Macrocell MAX EPLD(192-宏單元 MAX EPLD) |
| 中文描述： | 192個宏單元最大可編程邏輯器件（192 -宏單元最大可編程邏輯器件） |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 217K |
| 代理商： | CY7C341 |
CY7C341
7
t
H
Input Hold Time from
Synchronous Clock Input
[6]
Com
’
l
Mil
0
0
0
0
0
0
ns
t
WH
Synchronous Clock Input
High Time
Com
’
l
Mil
Com
’
l
Mil
8
8
8
8
10
10
10
10
12.5
12.5
12.5
12.5
ns
t
WL
Synchronous Clock Input
Low Time
ns
t
RW
Asynchronous Clear Width
[3, 6]
Com
’
l
Mil
Com
’
l
Mil
25
25
30
30
35
35
ns
t
RO
Asynchronous Clear to
Registered Output Delay
[5]
25
25
30
30
35
35
ns
t
RR
Asynchronous Clear Recovery
[3, 7]
Com
’
l
Mil
Com
’
l
Mil
25
25
25
25
30
30
30
30
35
35
35
35
ns
t
PW
Asynchronous Preset Width
[3, 6]
ns
t
PR
Asynchronous Preset Recovery
Time
[3, 6]
Com
’
l
Mil
Com
’
l
Mil
25
25
30
30
35
35
ns
t
PO
Asynchronous Preset to
Registered Output Delay
[6]
25
25
30
30
35
35
ns
t
CF
Synchronous Clock to Local
Feedback Input
[3, 13]
Com
’
l
Mil
Com
’
l
Mil
3
3
3
3
5
5
ns
t
P
External Synchronous Clock Period
(1/f
MAX3
)
[3]
16
16
20
20
25
25
ns
f
MAX1
External Feedback Maximum
Frequency (1/(t
CO1
+
t
S1
))
[3, 14]
Com
’
l
Mil
Com
’
l
Mil
34.5
34.5
55.5
55.5
27.7
27.7
43
43
22.2
22.2
33
33
MHz
f
MAX2
Internal Local Feedback Maximum
Frequency, lesser of (1/(t
S1
+ t
CF
))
or (1/t
CO1
)
[3, 15]
Data Path Maximum Frequency, least
of 1/(t
WL
+ t
WH
), 1/(t
S1
+ t
H
), or (1/t
CO1
)
[3,
16]
MHz
f
MAX3
Com
’
l
Mil
62.5
62.5
50
50
40.0
40.0
MHz
f
MAX4
Maximum Register Toggle Frequency
(1/(t
WL
+ t
WH
))
[3, 17]
Com
’
l
62.5
50
40.0
MHz
Mil
Com
’
l
Mil
62.5
3
3
50
3
3
40.0
3
3
t
OH
Output Data Stable Time from Syn-
chronous Clock Input
[3, 18]
ns
Notes:
13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array
input. This delay plus the register set-up time, t
, is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within
the same LAB. This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can
operate. It is assumed that all data inputs and feedback signals are applied to dedicated inputs. All feedback is assumed to be local originating within the same
LAB.
15. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states
must also control external points, this frequency can still be observed as long as this frequency is less than 1/t
.
16. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data
input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, t
is the appropriate t
for calculation.
17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycle by a clock
signal applied to the dedicated clock input pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
External Synchronous Switching Characteristics
Over the Operating Range
[6]
(continued)
Parameter
Description
7C341-25
Min.
7C341-30
Min.
7C341-35
Min.
Max
Max
Max
Unit
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| CY7C34125JI | 制造商:Cypress Semiconductor 功能描述: |
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| CY7C341-30JC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 3.75K Gates 192 Macro Cells 0.8um Technology 5V 84-Pin PLCC |
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