參數(shù)資料
型號(hào)： CY7C341
廠商： Cypress Semiconductor Corp.
英文描述： 192-Macrocell MAX EPLD(192-宏單元 MAX EPLD)
中文描述： 192個(gè)宏單元最大可編程邏輯器件（192 -宏單元最大可編程邏輯器件）
文件頁(yè)數(shù)： 1/15頁(yè)
文件大?。?/td> 217K
代理商： CY7C341
192-Macrocell MAX EPLD
CY7C341
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
December 9, 1999
408-943-2600
Features
192 macrocells in 12 LABs
8 dedicated inputs, 64 bidirectional I/O pin
0.8-micron double-metal CMOS EPROM technology
Programmable interconnect array
384 expander product terms
Available in 84-pin HLCC, PLCC, and PGA packages
Functional Description
The CY7C341 is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX architecture is
100% user-configurable, allowing the devices to accommo-
date a variety of independent logic functions.
The 192 macrocells in the CY7C341 are divided into 12 Logic
Array Blocks (LABs), 16 per LAB. There are 384 expander
product terms, 32 per LAB, to be used and shared by the mac-
rocells within each LAB. Each LAB is interconnected with a
programmable interconnect array, allowing all signals to be
routed throughout the chip.
The speed and density of the CY7C341 allows them to be
used in a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 37 times the functionality
of 20-pin PLDs, the CY7C341 allows the replacement of over
75 TTL devices. By replacing large amounts of logic, the
CY7C341 reduces board space and part count, and increases
system reliability.
Each LAB contains 16 macrocells. In LABs A, F, G, and L, 8
macrocells are connected to I/O pins and 8 are buried, while
for LABs B, C, D, E, H, I, J, and K, 4 macrocells are connected
to I/O pins and 12 are buried. Moreover, in addition to the I/O
and buried macrocells, there are 32 single product term logic
expanders in each LAB. Their use greatly enhances the capa-
bility of the macrocells without increasing the number of prod-
uct terms in each macrocell.
Logic Array Blocks
There are 12 logic array blocks in the CY7C341. Each LAB
consists of a macrocell array containing 16 macrocells, an ex-
pander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable in-
terconnect array so that they may be accessed by macrocells
in other LABs as well as the macrocells in the LAB in which
they are situated.
Externally, the CY7C341 provides 8 dedicated inputs, one of
which may be used as a system clock. There are 64 I/O pins
that may be individually configured for input, output, or bidirec-
tional data flow.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves intercon-
nect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed delay,
regardless of programmable interconnect array configuration,
simplifies design by assuring that internal signal skews or rac-
es are avoided. The result is ease of design implementation,
often in a single pass, without the multiple internal logic place-
ment and routing iterations required for a programmable gate
array to achieve design timing objectives.
Timing Delays
Timing delays within the CY7C341 may be easily determined
using
Warp2
or
Warp3
software. The CY7C341 has fixed
internal delays, allowing the user to determine the worst case
timing delays for any design. For complete timing information,
the
Warp3
software provides a timing simulator.
Design Recommendations
For proper operation, input and output pins must be con-
strained to the range GND < (V
IN
or V
OUT
) < V
CC
. Unused
inputs must always be tied to an appropriate logic level (either
V
CC
or GND). Each set of V
CC
and GND pins must be connect-
ed together directly at the device. Power supply decoupling
capacitors of at least 0.2
μ
F must be connected between V
CC
and GND. For the most effective decoupling, each V
CC
pin
should be separately decoupled to GND, directly at the device.
Decoupling capacitors should have good frequency response,
such as monolithic ceramic types.
Design Security
The CY7C341 contains a programmable design security fea-
ture that controls the access to the data programmed into the
device. If this programmable feature is used, a proprietary de-
sign implemented in the device cannot be copied or retrieved.
This enables a high level of design control to be obtained since
programmed data within EPROM cells is invisible. The bit that
controls this function, along with all other program data, may
be reset simply by erasing the device.
MAX is a registered trademark of Altera Corporation.
Warp
is a trademark of Cypress Semiconductor Corporation.
Warp2
, and
Warp3
are registered trademarks of Cypress Semiconductor Corporation.
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