參數(shù)資料
型號(hào): CY7C264
廠商: Cypress Semiconductor Corp.
英文描述: 8K x 8 Power-Switched and Reprogrammable PROM(8K x 8功率轉(zhuǎn)換和 可重復(fù)編程的PROM)
中文描述: 8K的× 8電源開(kāi)關(guān)和可重編程胎膜早破(8K的× 8功率轉(zhuǎn)換和可重復(fù)編程的可編程)
文件頁(yè)數(shù): 1/14頁(yè)
文件大?。?/td> 358K
代理商: CY7C264
8K x 8 Power-Switched and Reprogrammable PROM
CY7C261
CY7C263/CY7C264
Cypress Semiconductor Corporation
Document #: 38-04010 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 17, 2006
Features
CMOS for optimum speed/power
Windowed for reprogrammability
High speed
— 20 ns (Commercial)
— 25 ns (Military)
Low power
— 660 mW (Commercial)
— 770 mW (Military)
Super low standby power (7C261)
— Less than 220 mW when deselected
— Fast access: 20 ns
EPROM technology 100% programmable
Slim 300-mil or standard 600-mil packaging available
5V
±
10% V
CC
, commercial and military
Capable of withstanding greater than 2001V static
discharge
TTL-compatible I/O
Direct replacement for bipolar PROMs
Functional Description
The CY7C261, CY7C263, and CY7C264 are high-perfor-
mance 8192-word by 8-bit CMOS PROMs. When deselected,
the CY7C261 automatically powers down into a low-power
standby mode. It is packaged in a 300-mil-wide package. The
CY7C263 and CY7C264 are packaged in 300-mil-wide and
600-mil-wide packages respectively, and do not power down
when deselected. The reprogrammable packages are
equipped with an erasure window; when exposed to UV light,
these PROMs are erased and can then be reprogrammed.
The memory cells utilize proven EPROM floating-gate
technology and byte-wide intelligent programming algorithms.
The CY7C261, CY7C263, and CY7C264 are plug-in replace-
ments for bipolar devices and offer the advantages of lower
power, superior performance and programming yield. The
EPROM cell requires only 12.5V for the supervoltage and low
current requirements allow for gang programming. The
EPROM cells allow for each memory location to be tested
100%, as each location is written into, erased, and repeatedly
exercised prior to encapsulation. Each PROM is also tested
for AC performance to guarantee that after customer
programming the product will meet DC and AC specification
limits.
Read is accomplished by placing an active LOW signal on CS.
The contents of the memory location addressed by the
address line (A
0
A
12
) will become available on the output lines
(O
0
O
7
).
For an 8K x 8 Registered PROM, see theCY7C265.
Logic Block Diagram
Pin Configurations
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
ADDRESS
DECODER
PMABLE
ARRAY
MULTI-
PLEXER
POWER DOWN
(7C261)
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
CS
GND
1
2
3
4
5
6
7
8
9
10
11
12
14
13
15
16
20
19
18
17
21
24
23
22
Top View
DIP/Flatpack
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
A
7
O
3
V
CC
A
8
A
9
A
10
CS
A
11
O
7
O
6
O
5
O
4
O
2
A
12
28
4
5
6
7
8
9
10
1112
3 2 1
27
1314151617
26
25
24
23
22
21
20
19
A
VC
G
A
A
O
O
O
0
Top View
18
O
O
NC
A
0
A
4
A
3
A
2
A
1
A
10
CS
A
11
A
12
NC
O
7
O
6
A
A
N
N
7C261
7C263
7C261
7C263
O
COLUMN
ADDROW
LCC/PLCC (Opaque Only)
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