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參數(shù)資料
| 型號： | CY7C287 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 64K x 8 Reprogrammable Registered PROM(64K x 8重復(fù)編程的寄存式PROM) |
| 中文描述： | 64KX8的可再編程注冊胎膜早破（64KX8的重復(fù)編程的寄存式可編程） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 223K |
| 代理商： | CY7C287 |
64K x 8 Reprogrammable Registered PROM
CY7C287
Cypress Semiconductor Corporation
3901 North First Street
San Jose
September 1994 – Revised December 1994
CA 95134
408-943-2600
1CY7C287
Features
CMOS for optimum speed/power
Windowed for reprogrammability
High speed
—t
SA
= 45 ns
—t
CO
= 15 ns
Low power
—120 mA
On-chip, edge-triggered output registers
Programmable synchronous or asynchronous output
enable
EPROM technology, 100% programmable
5V
±
10% V
CC
, commercial and military
TTL-compatible I/O
Slim 300-mil package
Capable of withstanding >2001V static discharge
Functional Description
The CY7C287 is a high-performance 64K x 8 CMOS PROM.
The CY7C287 is equipped with an output register and an out-
put enable that can be programmed to be synchronous (E
S
) or
asynchronous (E). It is available in a 28-pin, 300-mil package.
The address set-up time is 45 ns and the time from clock HIGH
to output valid is 15 ns.
The CY7C287 is available in a cerDIP package equipped with
an erasure window to provide reprogrammability. When ex-
posed to UV light, the PROM is erased and can be repro-
grammed. The memory cells utilize proven EPROM float-
ing-gate technology and byte-wide intelligent programming
algorithms.
The CY7C287 offers the advantage of low power, superior per-
formance, and programming yield. The EPROM cell requires
only 12.5V for the supervoltage and low current requirements
allow for gang programming. The EPROM cells allow for each
memory location to be 100% tested with each cell being pro-
grammed, erased, and repeatedly exercised prior to encapsu-
lation. Each PROM is also tested for AC performance to guar-
antee that the product will meet DC and AC specification
limits after customer programming.
Reading the CY7C287 is accomplished by placing an active
LOW signal on E/E
S
. The contents of the memory location
addressed by the address lines (A
0
A
15
) will become
available on the output lines (O
0
O
7
) on the next rising of
CP.
Logic Block Diagram
Pin Configurations
CerDIP
C287-1
C287-2
12
13
31
4
5
6
7
8
9
10
11
3 2 1
30
14151617
25
24
23
22
21
Top View
LCC/PLCC
181920
26
28
29
32
GND
O
0
7C287
A
5
A
4
A
3
NC
A
2
A
1
A
0
S
O
GND
A
13
A
14
A
15
NC
E/E
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
17
18
19
20
24
23
22
21
25
28
27
26
Top View
7C287
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
0
O
1
O
2
GND
V
CC
A
10
A
11
A
12
A
13
A
14
A
15
CP
E/E
S
O
7
O
6
O
5
O
4
O
3
C287-3
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
8 MULTI-
PLEXER
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
E/E
S
CP
OE
REGISTER
PROGRAMMABLE
MULTIPLEXER
512x 1024
PRMABLE
ARRAY
S8
AMPS
8-BIT
TRIGGERED
REGISTER
X
Y
ROW
ADDRESS
COLUMN
ADDRESS
ADDRESS
DECODER
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