參數(shù)資料
型號： CY7C1524AV18-250BZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
中文描述： 2M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù)： 6/28頁
文件大小： 1133K
代理商： CY7C1524AV18-250BZXI
PRELIMINARY
CY7C1522AV18
CY7C1529AV18
CY7C1523AV18
CY7C1524AV18
Document #: 001-06981 Rev. *B
Page 6 of 28
Pin Definitions
Pin Name
D
[x:0]
I/O
Input-
Pin Description
Synchronous
Data Input signals, sampled on the rising edge of K and K clocks during valid Write
operations
.
CY7C1522AV18
D
[7:0]
CY7C1529AV18
D
[8:0]
CY7C1523AV18
D
[17:0]
CY7C1524AV18
D
[35:0]
Synchronous Load
: This input is brought LOW when a bus cycle sequence is to be defined.
This definition includes address and Read/Write direction. All transactions operate on a burst of
2 data (one period of bus activity).
Nibble Write Select 0, 1
active LOW (CY7C1522AV18 only)
. Sampled on the rising edge of
the K and K clocks during Write operations. Used to select which nibble is written into the device
during the current portion of the Write operations. Nibbles not written remain unaltered.
NWS
0
controls D
[8:0]
and NWS
1
controls D
[7:4]
.
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble
Write Select will cause the corresponding nibble of data to be ignored and not written into the
device.
Byte Write Select 0, 1, 2, and 3
active LOW
. Sampled on the rising edge of the K and K
clocks during Write operations. Used to select which byte is written into the device during the
current portion of the Write operations. Bytes not written remain unaltered.
CY7C1529AV18
BWS
0
controls D
[3:0]
and BWS
1
controls D
[7:4]
.
CY7C1523AV18
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1524AV18
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and
BWS
3
controls D
[35:27]
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs
. Sampled on the rising edge of the K clock during active Read and Write
operations. These address inputs are multiplexed for both Read and Write operations. Internally,
the device is organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1522AV18, 8M x 9 (2 arrays
each of 4M x 8) for CY7C1529AV18,4M x 18 (two arrays each of 2Mx 18) for CY7C1523AV18
and 2M x 36 (2 arrays each of 1M x 36) for CY7C1524AV18. Therefore only 22 address inputs
are needed to access the entire memory array of CY7C1522AV18 and CY7C1529AV18, 21
address inputs for CY7C1523AV18, and 20 address inputs for CY7C1524AV18. These inputs
are ignored when the appropriate port is deselected.
Data Output signals
. These pins drive out the requested data during a Read operation. Valid
data is driven out on the rising edge of both the C and C clocks during Read operations or K
and K when in single clock mode. When Read access is deselected, Q
[x:0]
are automatically
tri-stated.
CY7C1522AV18
Q
[7:0]
CY7C1529AV18
Q
[8:0]
CY7C1523AV18
Q
[17:0]
CY7C1524AV18
Q
[35:0]
Synchronous Read/Write Input
: When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up
and hold times around edge of K.
Positive Input clock for output data
. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
Negative Input clock for output data
. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various devices
on the board back to the controller. See application example for further details.
Positive Input Clock Input
. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated
on the rising edge of K.
Negative Input Clock Input
. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q
[x:0]
when in single clock mode.
LD
Input-
Synchronous
NWS
[1:0]
Input-
Synchronous
BWS
[3:0]
Input-
Synchronous
A
Input-
Synchronous
Q
[x:0]
Output-
Synchronous
R/W
Input-
Synchronous
C
Input-
Clock
C
Input-
Clock
K
Input-
Clock
K
Input-
Clock
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1524AV18-278BZC 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1524AV18-278BZI 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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CY7C1524AV18-278BZXI 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1525JV18250BZC 制造商:Cypress Semiconductor 功能描述:
CY7C1525JV18-250BZC 功能描述:靜態(tài)隨機存取存儲器 8M x 9 1.8V QDR-II 靜態(tài)隨機存取存儲器 Two-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1525JV18-250BZCES 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述:
CY7C1525JV18-250BZXC 功能描述:靜態(tài)隨機存取存儲器 8M x 9 1.8V QDR-II 靜態(tài)隨機存取存儲器 Two-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1525KV18-250BZC 功能描述:靜態(tài)隨機存取存儲器 72MB (8Mx9) 1.8v 250MHz QDR II 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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