參數(shù)資料
型號(hào)： CY7C1523AV18-300BZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
中文描述： 4M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 15/28頁(yè)
文件大小： 1133K
代理商： CY7C1523AV18-300BZXI
PRELIMINARY
CY7C1522AV18
CY7C1529AV18
CY7C1523AV18
CY7C1524AV18
Document #: 001-06981 Rev. *B
Page 15 of 28
TAP Controller Block Diagram
TAP Electrical Characteristics
Over the Operating Range
[11, 15, 17]
Parameter
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Description
Test Conditions
I
OH
=
2.0 mA
I
OH
=
100
μ
A
I
OL
= 2.0 mA
I
OL
= 100
μ
A
Min.
1.4
1.6
Max.
Unit
V
V
V
V
V
V
μ
A
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input and OutputLoad Current
0.4
0.2
0.65V
DD
–0.3
–5
V
DD
+ 0.3
0.35V
DD
5
GND
≤
V
I
≤
V
DD
TAP AC Switching Characteristics
Over the Operating Range
[12, 13]
Parameter
t
TCYC
t
TF
t
TH
t
TL
Set-up Times
t
TMSS
t
TDIS
t
CS
Notes:
11. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
12.t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
13.Test conditions are specified using the load in TAP AC test conditions. t
R
/t
F
= 1 ns.
Description
Min.
50
Max.
Unit
ns
MHz
ns
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
TCK Clock LOW
20
20
20
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
ns
0
0
1
2
.
.
29
30
31
Boundary Scan Register
Identification Register
0
1
2
.
.
.
.
108
0
1
2
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1524AV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1524AV18-167BZC 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1524AV18-167BZI 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1524AV18-167BZXC 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1524AV18-167BZXI 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1523JV18-300BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4Mbx18 72Mb 1.7-1.9V 300 MHz 2 WORD BURST RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1523KV18-250BZ 制造商:Cypress Semiconductor 功能描述:
CY7C1523KV18-250BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (4Mx18) 1.8v 250MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1523V18-167BZCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 4MX18 0.5NS 165FBGA - Bulk
CY7C1523V18-200BZCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Bulk
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