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參數(shù)資料
| 型號(hào)： | CY7C1523AV18-300BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| 中文描述： | 4M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 10/28頁(yè) |
| 文件大?。?/td> | 1133K |
| 代理商： | CY7C1523AV18-300BZXI |
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PRELIMINARY
CY7C1522AV18
CY7C1529AV18
CY7C1523AV18
CY7C1524AV18
Document #: 001-06981 Rev. *B
Page 10 of 28
Write Cycle Descriptions
(CY7C1522AV18 and CY7C1523AV18)
[3, 9]
BWS
0
/NWS
0
L
BWS
1
/NWS
1
L
K
K
-
Comments
L-H
During the Data portion of a Write sequence
:
CY7C1522AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1523AV18
both bytes (D
[17:0]
) are written into the device.
L-H During the Data portion of a Write sequence
:
CY7C1522AV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1523AV18
both bytes (D
[17:0]
) are written into the device.
-
During the Data portion of a Write sequence
:
CY7C1522AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1523AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
L-H During the Data portion of a Write sequence
:
CY7C1522AV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1523AV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
–
During the Data portion of a Write sequence
:
CY7C1522AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1523AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
L-H During the Data portion of a Write sequence
:
CY7C1522AV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1523AV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
–
No data is written into the devices during this portion of a Write operation.
L-H No data is written into the devices during this portion of a Write operation.
L
L
-
L
H
L-H
L
H
-
H
L
L-H
H
L
–
H
H
H
H
L-H
–
Note:
9. Assumes a Write cycle was initiated per the Write Cycle Description Truth Table. BWS
, BWS
in the case of CY7C1522AV18 and CY7C1523AV18 and also
BWS
2
, BWS
3
in the case of CY7C1524AV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1524AV18 | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1524AV18-167BZC | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1524AV18-167BZI | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1524AV18-167BZXC | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
| CY7C1524AV18-167BZXI | 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1523JV18-300BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4Mbx18 72Mb 1.7-1.9V 300 MHz 2 WORD BURST RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1523KV18-250BZ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1523KV18-250BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 72MB (4Mx18) 1.8v 250MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1523V18-167BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 4MX18 0.5NS 165FBGA - Bulk |
| CY7C1523V18-200BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 72MBIT 4MX18 0.45NS 165FBGA - Bulk |
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