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參數(shù)資料
| 型號： | CY7C1486V25-167BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| 中文描述： | 1M X 72 CACHE SRAM, 3.4 ns, PBGA209 |
| 封裝： | 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209 |
| 文件頁數(shù)： | 21/31頁 |
| 文件大小： | 530K |
| 代理商： | CY7C1486V25-167BGI |
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CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *G
Page 21 of 31
Switching Characteristics
Over the Operating Range
[14, 15]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Description
250 MHz
Min.
1
200 MHz
Min.
1
167 MHz
Min.
1
Unit
ms
Max.
Max.
Max.
V
DD
(Typical) to the first access
[16]
Clock Cycle Time
Clock HIGH
Clock LOW
4.0
2.0
2.0
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[17, 18, 19]
Clock to High-Z
[17, 18, 19]
OE LOW to Output Valid
OE LOW to Output Low-Z
[17, 18, 19]
OE HIGH to Output High-Z
[17, 18, 19]
3.0
3.0
3.4
ns
ns
ns
ns
ns
ns
ns
1.3
1.3
1.3
1.3
1.5
1.5
3.0
3.0
3.0
3.0
3.4
3.4
0
0
0
3.0
3.0
3.4
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
X
Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW, BWE, BW
X
Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
14.Timing reference level is 1.25V when V
= 2.5V and is 0.9V when V
DDQ
= 1.8V.
15.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
16.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
17.t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
18.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
19.This parameter is sampled and not 100% tested.
[+] Feedback
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