參數(shù)資料
型號: CY7C1483V33-100BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 2M x 36/4M x 18/1M x 72 Flow-through SRAM
中文描述: 4M X 18 CACHE SRAM, 8.5 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
文件頁數(shù): 11/30頁
文件大小: 638K
代理商: CY7C1483V33-100BZC
PRELIMINARY
CY7C1481V33
CY7C1483V33
CY7C1487V33
Document #: 38-05284 Rev. *A
Page 11 of 30
Write Cycle Descriptions
[1, 2]
Function (CY7C1481V33)
GW
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
BWE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
BW
d
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
BW
c
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
BW
b
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
BW
a
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
Read
Read
Write Byte 0
DQa
Write Byte 1
DQb
Write Bytes 1, 0
Write Byte 2
DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3
DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
Write All Bytes
Function (CY7C1483V33)
GW
1
1
1
1
1
0
BWE
1
0
0
0
0
X
BW
b
X
1
1
0
0
X
BW
a
X
1
0
1
0
X
Read
Read
Write Byte 0
DQ
[7:0]
and DP
0
Write Byte 1
DQ
[15:8]
and DP
1
Write All Bytes
Write All Bytes
Function (CY7C1487V33)
[5]
GW
1
1
1
1
0
BWE
1
0
0
0
X
BW
x
X
Read
Read
Write Byte X
Write All Bytes
Write All Bytes
All BW
= 1
0
All BW
= 0
X
Note:
5.
BWx represents any byte write signal BW[0..7]. To enable any byte write BWx, a low logic signal should be applied at clock rise. Any number of byte writes
can be enabled at the same time for any given write.
相關PDF資料
PDF描述
CY7C1483V33-117AC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
CY7C1483V33-117BGC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
CY7C1483V33-117BZC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
CY7C1483V33-133AC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
CY7C1483V33-133BGC 2M x 36/4M x 18/1M x 72 Flow-through SRAM
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