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參數(shù)資料
| 型號： | CY7C1482V25-200BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| 中文描述： | 4M X 18 CACHE SRAM, 3 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165 |
| 文件頁數(shù)： | 7/31頁 |
| 文件大小： | 530K |
| 代理商： | CY7C1482V25-200BZXC |
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CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *G
Page 7 of 31
Pin Definitions
Pin Name
A
0
, A
1
, A
I/O
Input-
Description
Synchronous
Address Inputs used to select one of the address locations
. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3
are sampled
active. A1: A0 are fed to the two-bit counter.
Byte Write Select Inputs, active LOW
. Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK.
BW
A
, BW
B
, BW
C
,
BW
D
, BW
E
, BW
F
,
BW
G
, BW
H
GW
Input-
Synchronous
Input-
Synchronous
Global Write Enable Input, active LOW
. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW
X
and BWE).
Byte Write Enable Input, active LOW
. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Clock Input
. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is
HIGH. CE
1
is sampled only when a new external address is loaded.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device. CE
2
is sampled only when
a new external address is loaded.
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and
CE
2
to select/deselect the device. CE
3
is sampled only when
a new external address is loaded.
Output Enable, asynchronous input, active LOW
. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW
. When
asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW
.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW
.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ “sleep” Input, active HIGH
. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQP
X
are placed in a tri-state
condition.
Power supply inputs to the core of the device
.
Ground for the core of the device
.
Ground for the I/O circuitry
.
I/O Power Supply
Power supply for the I/O circuitry
.
Input Static
Selects Burst Order
. When tied to GND selects linear burst sequence. When tied to
V
DD
or left floating selects interleaved burst sequence. This is a strap pin and should
remain static during device operation. Mode Pin has an internal pull-up.
BWE
Input-
Synchronous
Input-
Clock
Input-
Synchronous
CLK
CE
1
CE
2
Input-
Synchronous
CE
3
Input-
Synchronous
OE
Input-
Asynchronous
ADV
Input-
Synchronous
Input-
Synchronous
ADSP
ADSC
Input-
Synchronous
ZZ
Input-
Asynchronous
DQs, DQPs
I/O-
Synchronous
V
DD
V
SS
V
SSQ
V
DDQ
MODE
Power Supply
Ground
I/O Ground
[+] Feedback
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