參數(shù)資料
型號(hào): CY7C1482V25-200BZXC
廠(chǎng)商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): DRAM
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
中文描述: 4M X 18 CACHE SRAM, 3 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
文件頁(yè)數(shù): 15/31頁(yè)
文件大小: 530K
代理商: CY7C1482V25-200BZXC
CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *G
Page 15 of 31
2.5V TAP AC Test Conditions
Input pulse levels................................................ V
SS
to 2.5V
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
2.5V TAP AC Output Load Equivalent
1.8V TAP AC Test Conditions
Input pulse levels..................................... 0.2V to V
DDQ
– 0.2
Input rise and fall time ......................................................1ns
Input timing reference levels...........................................0.9V
Output reference levels ..................................................0.9V
Test load termination supply voltage ..............................0.9V
1.8V TAP AC Output Load Equivalent
TDO
1.25V
20pF
Z = 50
50
TDO
0.9V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < T
A
< +70°C; V
DD
= 2.5V ±0.125V unless otherwise noted)
[10]
Parameter
Description
V
OH1
Output HIGH Voltage
V
OH2
Output HIGH Voltage
Test Conditions
Min.
1.7
2.1
1.6
Max.
Unit
V
V
V
V
V
V
V
V
V
V
μ
A
I
OH
= –1.0 mA
I
OH
= –100
μ
A
V
DDQ
= 2.5V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
OL1
V
OL2
Output LOW Voltage
Output LOW Voltage
I
OL
= 1.0 mA
I
OL
= 100
μ
A
0.4
0.2
0.2
V
IH
Input HIGH Voltage
1.7
1.26
–0.3
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.7
0.36
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND
V
I
V
DDQ
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
Architecture/Memory
Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code
(11:1)
ID Register Presence
Indicator (0)
CY7C1480V25
(2M x36)
000
01011
000000
CY7C1482V25
(4M x 18)
000
01011
000000
CY7C1486V25
(1M x72)
000
01011
000000
Description
Describes the version number
Reserved for internal use
Defines memory type and
architecture
Defines width and density
Allows unique identification of
SRAM vendor
Indicates the presence of an
ID register
100100
00000110100
010100
00000110100
110100
00000110100
1
1
1
Note:
10.All voltages referenced to V
SS
(GND).
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