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參數(shù)資料
| 型號： | CY7C1482V25-167AXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| 中文描述： | 4M X 18 CACHE SRAM, 3.4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100 |
| 文件頁數(shù)： | 31/31頁 |
| 文件大?。?/td> | 530K |
| 代理商： | CY7C1482V25-167AXI |
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CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *G
Page 31 of 31
Document History Page
Document Title: CY7C1480V25/CY7C1482V25/CY7C1486V25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Document Number: 38-05282
Orig. of
Change
**
114670
08/06/02
PKS
New Data Sheet
*A
118281
01/21/03
HGK
Changed t
CO
from 2.4 to 2.6 ns for 250 MHz
Updated features on page 1 for package offering
Removed 300 MHz offering
Updated Ordering Information
Changed Advanced Information to Preliminary
*B
233368
See ECN
NJY
Changed timing diagrams
Changed logic block diagrams
Modified Functional Description
Modified “Functional Overview” section
Added boundary scan order for all packages
Included thermal numbers and capacitance values for all packages
Included IDD and ISB values
Removed 250-MHz speed grade offering and included 225 MHz speed bin
Changed package outline for 165FBGA package and 209-ball BGA package
Removed 119-BGA package offering
*C
299452
See ECN
SYT
Removed 225-MHz offering and included 250-MHz speed bin
Changed t
CYC
from 4.4 ns to 4.0 ns for 250-MHz Speed Bin
Changed
Θ
JA
from 16.8 to 24.63
°
C/W and
Θ
JC
from 3.3 to 2.28
°
C/W for 100
TQFP Package on Page # 20
Added lead-free information for 100-Pin TQFP, 165 FBGA and 209 BGA
Packages
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
*D
323039
See ECN
PCI
Unshaded 200 and 167 MHz speed bin in the AC/DC Table and Selection
Guide
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added Address Expansion pins in the Pin Definitions Table
Added Truth Table and Note# 7 for CY7C1486V25 on page# 11
Modified V
OL
, V
OH
Test Conditions
Added Industrial temperature range
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
*E
416193
See ECN
NXR
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of I
X
from Input Load Current to Input Leakage
Current on page# 19
Changed the I
X
current values of MODE on page # 19 from -5
μ
A and 30
μ
A
to -30
μ
A and 5
μ
A
Changed the I
X
current values of ZZ on page # 19 from -30
μ
A and 5
μ
A
to -5
μ
A and 30
μ
A
Changed V
IH
< V
DD
to V
IH
< V
DD
on page # 19
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated the Ordering Information Table
*F
470723
See ECN
VKN
Added the Maximum Rating for Supply Voltage on V
DDQ
Relative to GND
Changed t
TH
, t
TL
from 25 ns to 20 ns and t
TDOV
from 5 ns to 10 ns in TAP
AC Switching Characteristics table
Updated the Ordering Information table
*G
486690
See ECN
VKN
Corrected the typo in the 209-Ball FBGA pinout.
(Corrected the ball name H9 to V
SS
from V
SSQ
).
REV.
ECN NO.
Issue Date
Description of Change
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1482V25-167BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1486V25-250BGI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1486V25-250BGXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1486V25-250BGXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1480V25_06 | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
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