- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379077 > CY7C1482V25-167AXI (CYPRESS SEMICONDUCTOR CORP) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM PDF資料下載
參數(shù)資料
| 型號： | CY7C1482V25-167AXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| 中文描述： | 4M X 18 CACHE SRAM, 3.4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100 |
| 文件頁數(shù)： | 21/31頁 |
| 文件大?。?/td> | 530K |
| 代理商： | CY7C1482V25-167AXI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *G
Page 21 of 31
Switching Characteristics
Over the Operating Range
[14, 15]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
ADVH
t
WEH
t
DH
t
CEH
Description
250 MHz
Min.
1
200 MHz
Min.
1
167 MHz
Min.
1
Unit
ms
Max.
Max.
Max.
V
DD
(Typical) to the first access
[16]
Clock Cycle Time
Clock HIGH
Clock LOW
4.0
2.0
2.0
5.0
2.0
2.0
6.0
2.4
2.4
ns
ns
ns
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[17, 18, 19]
Clock to High-Z
[17, 18, 19]
OE LOW to Output Valid
[17, 18, 19]
OE HIGH to Output High-Z
[17, 18, 19]
3.0
3.0
3.4
ns
ns
ns
ns
ns
ns
ns
1.3
1.3
1.3
1.3
1.5
1.5
3.0
3.0
3.0
3.0
3.4
3.4
0
0
0
3.0
3.0
3.4
Address Set-up Before CLK Rise
ADSC, ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
X
Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW, BWE, BW
X
Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
14.Timing reference level is 1.25V when V
= 2.5V and is 0.9V when V
DDQ
= 1.8V.
15.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
16.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
17.t
, t
, t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
18.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
19.This parameter is sampled and not 100% tested.
[+] Feedback
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C1482V25-167BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1486V25-250BGI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1486V25-250BGXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1486V25-250BGXI | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
| CY7C1480V25_06 | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C148-35PC | 功能描述:1KX4 18-PIN POWER-DOWN SRAM RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應商設備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C148-45DC | 制造商:Cypress Semiconductor 功能描述:Static RAM, 1Kx4, 18 Pin, Ceramic, DIP |
| CY7C148-45PC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1484BV25-250AXI | 制造商:Cypress Semiconductor 功能描述:SYNC - Trays 制造商:Cypress Semiconductor 功能描述:IC SRAM 72MBIT 250MHZ 100TQFP 制造商:Cypress Semiconductor 功能描述:TRAY / Sync SRAMs |
| CY7C1484BV33-250BZI | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。