參數(shù)資料
型號: CY7C1480V25-167AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
中文描述: 2M X 36 CACHE SRAM, 3.4 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100
文件頁數(shù): 19/31頁
文件大?。?/td> 530K
代理商: CY7C1480V25-167AXC
CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *G
Page 19 of 31
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................–55
°
C to +125
°
C
Supply Voltage on V
DD
Relative to GND........–0.3V to +3.6V
Supply Voltage on V
DDQ
Relative to GND ......–0.3V to +V
DD
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage ...................................–0.5V to V
DD
+ 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
DD
V
DDQ
1.7V to
V
DD
2.5V
–5%/+5%
Electrical Characteristics
Over the Operating Range
[11, 12]
Parameter
V
DD
V
DDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
2.375
2.375
1.7
2.0
1.6
Max.
2.625
V
DD
1.9
Unit
V
V
V
V
V
V
V
V
V
V
V
μ
A
for 2.5V I/O
for 1.8V I/O
for 2.5V I/O, I
OH
= –1.0 mA
for 1.8V I/O, I
OH
= –100
μ
A
for 2.5V I/O, I
OL
= 1.0 mA
for 1.8V I/O, I
OL
= 100
μ
A
for 2.5V I/O
for 1.8V I/O
for 2.5V I/O
for 1.8V I/O
GND
V
I
V
DDQ
V
OH
Output HIGH Voltage
V
OL
Output LOW Voltage
0.4
0.2
V
IH
Input HIGH Voltage
[11]
1.7
1.26
–0.3
–0.3
–5
V
DD
+ 0.3V
V
DD
+ 0.3V
0.7
0.36
5
V
IL
Input LOW Voltage
[11]
I
X
Input Leakage Current
except ZZ and MODE
Input Current of MODE
Input = V
SS
Input = V
DD
Input = V
SS
Input = V
DD
–30
μ
A
μ
A
μ
A
μ
A
μ
A
mA
mA
mA
mA
mA
mA
mA
5
Input Current of ZZ
–5
30
5
450
450
400
200
200
200
120
I
OZ
I
DD
Output Leakage Current GND
V
I
V
DDQ,
Output Disabled
V
DD
Operating Supply
Current
f = f
MAX
= 1/t
CYC
–5
V
DD
= Max., I
OUT
= 0 mA,
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
I
SB1
Automatic CE
Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
f = f
MAX
= 1/t
CYC
I
SB2
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
V
DD
= Max, Device Deselected,
V
IN
0.3V or V
IN
> V
DDQ
– 0.3V,
f = 0
V
DD
= Max, Device Deselected, or
V
IN
0.3V or V
IN
> V
DDQ
– 0.3V
f = f
MAX
= 1/t
CYC
I
SB3
4.0-ns cycle, 250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
All speeds
200
200
200
135
mA
mA
mA
mA
I
SB4
Automatic CE
Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
, f = 0
Notes:
11. Overshoot: V
(AC) < V
+1.5V (Pulse width less than t
/2), undershoot: V
(AC) > –2V (Pulse width less than t
CYC
/2).
12.Power-up: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD.
[+] Feedback
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