參數(shù)資料
型號(hào)： CY7C1475V25-100BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： DRAM
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
中文描述： 1M X 72 ZBT SRAM, 8.5 ns, PBGA209
封裝： 14 X 22 MM, 1.76 MM HEIGHT, FBGA-209
文件頁(yè)數(shù)： 16/30頁(yè)
文件大?。?/td> 373K
代理商： CY7C1475V25-100BGC
PRELIMINARY
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *E
Page 16 of 30
1.8V TAP AC Test Conditions
Input pulse levels.....................................0.2V to V
DDQ
– 0.2
Input rise and fall time..................................................... 1 ns
Input timing reference levels...........................................0.9V
Output reference levels...................................................0.9V
Test load termination supply voltage...............................0.9V
1.8V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels.................................................V
SS
to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels.........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage ............................1.25V
2.5V TAP AC Output Load Equivalent
TDO
0.9V
20pF
Z = 50
50
TDO
1.25V
20pF
Z = 50
50
TAP DC Electrical Characteristics And Operating Conditions
(0°C < T
A
< +70°C; V
DD
= 2.375 to 2.625 unless otherwise noted)
[12]
Parameter
Description
V
OH1
Output HIGH Voltage
V
OH2
Output HIGH Voltage
Test Conditions
Min.
2.0
2.1
1.6
Max.
Unit
V
V
V
V
V
V
V
V
V
V
μA
I
OH
= –1.0 mA, V
DDQ
= 2.5V
I
OH
= –100 μA
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
DDQ
= 2.5V
V
DDQ
= 1.8V
V
OL1
V
OL2
Output LOW Voltage
Output LOW Voltage
I
OL
= 1.0 mA
I
OL
= 100 μA
0.4
0.2
0.2
V
IH
Input HIGH Voltage
1.7
1.26
–0.3
–0.3
–5
V
DD
+ 0.3
V
DD
+ 0.3
0.7
0.36
5
V
IL
Input LOW Voltage
I
X
Input Load Current
GND < V
IN
< V
DDQ
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
Architecture/Memory
Type(23:18)
Bus Width/Density(17:12)
Cypress JEDEC ID Code
(11:1)
ID Register Presence
Indicator (0)
CY7C1471V25
(2MX36)
000
01011
001001
CY7C1473V25
(4MX18)
000
01011
001001
CY7C1475V25
(1MX72)
000
01011
001001
Description
Describes the version number
Reserved for internal use
Defines memory type and architecture
100100
00000110100
010100
00000110100
110100
00000110100 Allows unique identification of SRAM
vendor
1
Indicates the presence of an ID register
Defines width and density
1
1
Note:
12.All voltages referenced to V
SS
(GND).
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