參數(shù)資料
型號： CY7C1474V33-200BGXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
中文描述： 1M X 72 ZBT SRAM, 3 ns, PBGA209
封裝： 14 X 22 MM, 1.76 MM HEIGHT, LEAD FREE, FBGA-209
文件頁數(shù)： 21/28頁
文件大小： 378K
代理商： CY7C1474V33-200BGXC
PRELIMINARY
CY7C1470V33
CY7C1472V33
CY7C1474V33
Document #: 38-05289 Rev. *E
Page 21 of 28
Switching Characteristics
Over the Operating Range
[16, 17]
Parameter
t
Power[18]
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
OEV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Set-up Times
t
AS
t
DS
t
CENS
t
WES
t
ALS
t
CES
Hold Times
t
AH
t
DH
t
CENH
t
WEH
t
ALH
t
CEH
Shaded areas contain advance information.
Description
-250
-200
-167
Unit
ms
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
V
CC
(typical) to the First Access Read or Write
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
4.0
5.0
6.0
ns
MHz
ns
ns
250
200
167
2.0
2.0
2.0
2.0
2.2
2.2
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z
[19, 20, 21]
Clock to Low-Z
[19, 20, 21]
OE HIGH to Output High-Z
[19, 20, 21]
OE LOW to Output Low-Z
[19, 20, 21]
3.0
3.0
3.0
3.0
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
1.3
1.3
1.5
3.0
3.0
3.4
1.3
1.3
1.5
3.0
3.0
3.4
0
0
0
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
CEN Set-up Before CLK Rise
WE, BW
x
Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Address Hold After CLK Rise
Data Input Hold After CLK Rise
CEN Hold After CLK Rise
WE, BW
x
Hold After CLK Rise
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
16.Timing reference is 1.5V when V
3.3V and is 1.25V when V
2.5V.
17.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18.This part has a voltage regulator internally; t
power
is the time power needs to be supplied above V
DD
minimum initially, before a Read or Write operation can be
initiated.
19.t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21.This parameter is sampled and not 100% tested.
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