參數(shù)資料
型號： CY7C1473V33
廠商： Cypress Semiconductor Corp.
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
中文描述： 72兆位（2米x 36/4M x 18/1M × 72）流體系結(jié)構(gòu)，通過與總線延遲靜態(tài)存儲器
文件頁數(shù)： 8/30頁
文件大小： 373K
代理商： CY7C1473V33
PRELIMINARY
CY7C1471V25
CY7C1473V25
CY7C1475V25
Document #: 38-05287 Rev. *E
Page 8 of 30
Pin Definitions
Name
I/O
Input-
Description
A
0
, A
1
, A
Synchronous
Input-
Synchronous
Address Inputs used to select one of the address locations
. Sampled at the
rising edge of the CLK. A
[1:0]
are fed to the two-bit burst counter.
Byte Write Inputs, active LOW.
Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK.
BW
A
, BW
B
,
BW
C
, BW
D
,
BW
E
, BW
F
,
BW
G
, BW
H
WE
Input-
Synchronous
Input-
Synchronous
Write Enable Input, active LOW
. Sampled on the rising edge of CLK if CEN is
active LOW. This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input
. Used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
Clock Input
. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW
. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
, and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and
CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW
. Combined with the
synchronous logic block inside the device to control the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH,
I/O pins are tri-stated, and act as input data pins. OE is masked during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, when the device has been deselected.
Clock Enable Input, active LOW
. When asserted LOW the Clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
ZZ “Sleep” Input
. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved. During normal operation, this pin can
be connected to V
SS
or left floating.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQ
s
and DQP
X
are
placed in a tri-state condition.The outputs are automatically tri-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to
DQ
s
.
During write sequences, DQP
X
is controlled by BW
X
correspondingly.
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to V
DD
or left floating
selects interleaved burst sequence.
Power supply inputs to the core of the device
.
Power supply for the I/O circuitry
.
Ground for the device
.
ADV/LD
CLK
Input-
Clock
Input-
CE
1
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CE
2
CE
3
OE
CEN
Input-
Synchronous
ZZ
Input-
Asynchronous
DQ
s
I/O-
Synchronous
DQP
X
I/O-
Synchronous
Input Strap Pin
MODE
V
DD
V
DDQ
V
SS
Power Supply
I/O Power Supply
Ground
相關(guān)PDF資料
PDF描述
CY7C1471V25-100AXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25-133BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473V25-133BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1473V25-133BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
CY7C1471V25-100BZC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture
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