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參數(shù)資料
| 型號(hào)： | CY7C1472V33-200AXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| 中文描述： | 4M X 18 ZBT SRAM, 3 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大小： | 378K |
| 代理商： | CY7C1472V33-200AXC |
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PRELIMINARY
CY7C1470V33
CY7C1472V33
CY7C1474V33
Document #: 38-05289 Rev. *E
Page 9 of 28
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BW
. See Write Cycle Description table for details.
3. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ
s
and DQP
[a:d]
= Tri-state when
OE is inactive or when the device is deselected, and DQ
s
= data when OE is active.
Truth Table
[1, 2, 3, 4, 5, 6, 7]
Operation
Address
Used
None
None
CE
H
X
ZZ
L
L
ADV/LD
L
H
WE
X
X
BW
x
X
X
OE
X
X
CEN
CLK
L-H
L-H
DQ
Deselect Cycle
Continue
Deselect Cycle
Read Cycle
(Begin Burst)
Read Cycle
(Continue Burst)
NOP/Dummy Read
(Begin Burst)
Dummy Read
(Continue Burst)
Write Cycle
(Begin Burst)
Write Cycle
(Continue Burst)
NOP/Write Abort
(Begin Burst)
Write Abort
(Continue Burst)
Ignore Clock Edge
(Stall)
Sleep Mode
L
L
Tri-State
Tri-State
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
External
L
L
L
H
X
H
L
L-H
Tri-State
Next
X
L
H
X
X
H
L
L-H
Tri-State
External
L
L
L
L
L
X
L
L-H
Data In (D)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
None
L
L
L
L
H
X
L
L-H
Tri-State
Next
X
L
H
X
H
X
L
L-H
Tri-State
Current
X
L
X
X
X
X
H
L-H
-
None
X
H
X
X
X
X
X
X
Tri-State
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1472V33-200BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1472V33-200BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1472V33-250AXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1472V33-250BZC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
| CY7C1472V33-250BZXC | 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1472V33-200AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1472V33-200AXCT | 功能描述:IC SRAM 72MBIT 200MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:NoBL™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C1472V33-200BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4Mx18 3.3V NoBL PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1472V33-200BZIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 4Mx18 3.3V NoBL PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1472V33-250AXC | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 72MBIT 4MX18 3NS 100TQFP - Bulk |
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