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參數(shù)資料
| 型號(hào)： | CY7C1440AV33 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM(36-Mb (1M x 36/2M x 18/512K x 72)管道式同步SRAM) |
| 中文描述： | 36兆位（1米x 36/2M x 18/512K × 72）流水線同步靜態(tài)存儲(chǔ)器（36字節(jié)（100萬x 36/2M x 18/512K × 72）管道式同步靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 7/31頁 |
| 文件大?。?/td> | 531K |
| 代理商： | CY7C1440AV33 |
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document #: 38-05383 Rev. *E
Page 7 of 31
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH
. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3
to select/deselect the device. CE
2
is sampled only when a new external
address is loaded.
Chip Enable 3 Input, active LOW
. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and
CE
2
to select/deselect the device. Not available for AJ package version. Not
connected for BGA. Where referenced, CE
3
is assumed active throughout this document
for BGA. CE
3
is sampled only when a new external address is loaded.
Output Enable, asynchronous input, active LOW
. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
Advance Input signal, sampled on the rising edge of CLK, active LOW
. When asserted,
it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW
.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW
.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ “sleep” Input, active HIGH
. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines
. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQP
X
are placed in a tri-state condition.
Power supply inputs to the core of the device
.
Ground for the core of the device
.
Ground for the I/O circuitry
.
I/O Power Supply
Power supply for the I/O circuitry
.
Input-
Static
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
JTAG serial
output
Synchronous
on TQFP packages.
JTAG serial input
Synchronous
is not being utilized, this pin can be disconnected or connected to V
DD
. This pin is not
available on TQFP packages.
JTAG serial input
Synchronous
is not being utilized, this pin can be disconnected or connected to V
DD
. This pin is not
available on TQFP packages.
JTAG-
Clock
be connected to V
SS
. This pin is not available on TQFP packages.
–
No Connects
. Not internally connected to the die
–
No Connects
. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M
and NC/1G are address expansion pins are not internally connected to the die.
CE
3
Input-
Synchronous
OE
Input-
Asynchronous
ADV
Input-
Synchronous
Input-
Synchronous
ADSP
ADSC
Input-
Synchronous
ZZ
Input-
Asynchronous
DQs, DQP
X
I/O-
Synchronous
V
DD
V
SS
V
SSQ
V
DDQ
MODE
Power Supply
Ground
I/O Ground
Selects Burst Order
. When tied to GND selects linear burst sequence. When tied to V
DD
TDO
Serial data-out to the JTAG circuit
. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin should be disconnected. This pin is not available
TDI
Serial data-In to the JTAG circuit
. Sampled on the rising edge of TCK. If the JTAG feature
TMS
Serial data-In to the JTAG circuit
. Sampled on the rising edge of TCK. If the JTAG feature
TCK
Clock input to the JTAG circuitry
. If the JTAG feature is not being utilized, this pin must
NC
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
Pin Definitions
(continued)
Name
I/O
Description
相關(guān)PDF資料 |
PDF描述 |
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| CY7C1442AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM(36-Mb (1M x 36/2M x 18/512K x 72)管道式同步SRAM) |
| CY7C1446AV33 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM(36-Mb (1M x 36/2M x 18/512K x 72)管道式同步SRAM) |
| CY7C1460AV25 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| CY7C1464AV25 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
| CY7C1462AV25 | 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL Architecture(帶NoBL結(jié)構(gòu)的36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1440AV33-167AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx36 3.3V Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1440AV33-167AXCT | 功能描述:IC SRAM 36MBIT 167MHZ 100LQFP RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:移動(dòng) SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:133MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.95 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:帶卷 (TR) 其它名稱:557-1327-2 |
| CY7C1440AV33-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx36 3.3V Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1440AV33-167BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx36 3.3V Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1440AV33-167CKJ | 制造商:Cypress Semiconductor 功能描述: |
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