- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379075 > CY7C1418BV18-278BZXC (CYPRESS SEMICONDUCTOR CORP) 36-Mbit DDR-II SRAM 2-Word Burst Architecture PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1418BV18-278BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 2M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁(yè)數(shù)： | 10/28頁(yè) |
| 文件大?。?/td> | 1132K |
| 代理商： | CY7C1418BV18-278BZXC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)
PRELIMINARY
CY7C1416BV18
CY7C1427BV18
CY7C1418BV18
CY7C1420BV18
Document Number: 001-07033 Rev. *B
Page 10 of 28
Write Cycle Descriptions
(CY7C1416BV18 and CY7C1427BV18)
[2, 8]
BWS
0
,NWS
0
L
BWS
1
,NWS
1
L
K
K
–
Comments
L-H
During the Data portion of a Write sequence
:
CY7C1416BV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1427BV18
both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence
:
CY7C1416BV18
both nibbles (D
[7:0]
) are written into the device,
CY7C1427BV18
both bytes (D
[17:0]
) are written into the device.
During the Data portion of a Write sequence
:
CY7C1416BV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1427BV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
During the Data portion of a Write sequence
:
CY7C1416BV18
only the lower nibble (D
[3:0]
) is written into the device. D
[7:4]
will remain unaltered,
CY7C1427BV18
only the lower byte (D
[8:0]
) is written into the device. D
[17:9]
will remain unaltered.
During the Data portion of a Write sequence
:
CY7C1416BV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1427BV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
During the Data portion of a Write sequence
:
CY7C1416BV18
only the upper nibble (D
[7:4]
) is written into the device. D
[3:0]
will remain unaltered,
CY7C1427BV18
only the upper byte (D
[17:9]
) is written into the device. D
[8:0]
will remain unaltered.
No data is written into the devices during this portion of a Write operation.
No data is written into the devices during this portion of a Write operation.
L
L
–
L-H
L
H
L-H
–
L
H
–
L-H
H
L
L-H
–
H
L
–
L-H
H
H
H
H
L-H
–
–
L-H
Write Cycle Descriptions
(CY7C1420BV18)
[2, 8]
BWS
0
L
K
K
–
Comments
L-H
During the Data portion of a Write sequence
,
the single byte (D
[8:0]
) is written into the device.
During the Data portion of a Write sequence
,
the single byte (D
[8:0]
) is written into the device.
No data is written into the device during this portion of a Write operation.
No data is written into the device during this portion of a Write operation.
L
–
L-H
H
H
L-H
–
–
L-H
Note:
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS
0
, NWS
1
, BWS
0
, BWS
1
, BWS
2
,
and BWS
3
can be altered on different
portions of a Write cycle, as long as the set-up and hold requirements are achieved.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1418BV18-278BZXI | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18-300BZC | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18-300BZI | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18-300BZXC | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18-300BZXI | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1418JV18-300BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 DDR II Burst 2 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418JV18-300BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 DDR II Burst 2 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418KV18-250BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (2Mx18) 1.8v 250MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418KV18-250BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36864KB 1ms 430mA RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418KV18-250BZI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 36MB (2Mx18) 1.8v 250MHz DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。