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參數(shù)資料
| 型號： | CY7C1418AV18-250BZXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 2M X 18 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 456K |
| 代理商： | CY7C1418AV18-250BZXC |
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CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
Document Number: 38-05616 Rev. *D
Page 6 of 28
Pin Definitions
Pin Name
I/O
Pin Description
DQ
[x:0]
Input/Output-
Synchronous
Data Input/Output signals
. Inputs are sampled on the rising edge of K and K clocks during valid
Write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When read access is deselected, Q
[x:0]
are automatically tri-stated.
CY7C1416AV18
DQ
[7:0]
CY7C1420AV18
DQ
[8:0]
CY7C1427AV18
DQ
[17:0]
CY7C1418AV18
DQ
[35:0]
Synchronous Load
. This input is brought LOW when a bus cycle sequence is to be defined. This
definition includes address and Read/Write direction. All transactions operate on a burst of 2 data.
Nibble Write Select 0, 1
active LOW
(CY7C1416AV18 only)
. Sampled on the rising edge of the
K and K clocks during Write operations. Used to select which nibble is written into the device during
the current portion of the Write operations. Nibbles not written remain unaltered.
NWS
0
controls D
[3:0]
and NWS
1
controls D
[7:4]
.
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write
Select will cause the corresponding nibble of data to be ignored and not written into the device.
Byte Write Select 0, 1, 2, and 3
active LOW
. Sampled on the rising edge of the K and K clocks
during Write operations. Used to select which byte is written into the device during the current
portion of the Write operations. Bytes not written remain unaltered.
CY7C1420AV18
BWS
0
controls D
[8:0]
CY7C1418AV18
BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1420AV18
BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
, BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27]
.
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
Address Inputs
. These address inputs are multiplexed for both Read and Write operations. Inter-
nally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1416AV18 and 4M x 9
(2 arrays each of 2M x 9) for CY7C1420AV18, a single 2M x 18 array for CY7C1427AV18, and a
single array of 1M x 36 for CY7C1418AV18.
CY7C1416AV18 – Since the least significant bit of the address internally is a “0,” only 21 external
address inputs are needed to access the entire memory array.
CY7C1420AV18 – Since the least significant bit of the address internally is a “0,” only 21 external
address inputs are needed to access the entire memory array.
CY7C1427AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 21 address inputs are needed to access the entire memory array.
CY7C1418AV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 20 address inputs are needed to access the entire memory array. All the address inputs
are ignored when the appropriate port is deselected.
Synchronous Read/Write Input
. When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
Positive Output Clock Input
. C is used in conjunction with C to clock out the Read data from the
device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
Negative Output Clock Input
. C is used in conjunction with C to clock out the Read data from the
device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
Positive Input Clock Input
device and to drive out data through Q
[x:0]
when in single clock mode. All accesses are initiated on
the rising edge of K.
Negative Input Clock Input
. K is used to capture synchronous data being presented to the device
and to drive out data through Q
[x:0]
when in single clock mode.
CQ is referenced with respect to C
. This is a free running clock and is synchronized to the Input
clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to
K. The timings for the echo clocks are shown in the AC Timing table.
LD
Input-
Synchronous
Input-
Synchronous
NWS
0
,
NWS
1
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
Input-
Synchronous
A, A0
Input-
Synchronous
R/W
Input-
Synchronous
C
Input-
Clock
C
Input-
Clock
K
Input-
Clock
K
Input-
Clock
Output-
Clock
CQ
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1418AV18-267BZC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418AV18-267BZXC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418AV18-300BZC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418AV18-300BZXC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418BC | 制造商:Cypress Semiconductor 功能描述: |
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