參數(shù)資料
型號(hào)： CY7C1418AV18-167BZXC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 36-Mbit DDR-II SRAM 2-Word Burst Architecture
中文描述： 2M X 18 DDR SRAM, 0.5 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 456K
代理商： CY7C1418AV18-167BZXC
CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
Document Number: 38-05616 Rev. *D
Page 9 of 28
Notes:
1. The above application shows two DDR-II used.
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
↑
represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. On CY7C1418AV18 and CY7C1420AV18, “A1” represents address location latched by the devices when transaction was initiated and A2 represents the addresses
sequence in the burst. On CY7C1416AV18, “A1” represents A + ‘0’ and A2 represents A + ‘1’.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Application Example
[1]
Truth Table
[2, 3, 4, 5, 6, 7]
Operation
K
LD
L
R/W
L
DQ
DQ
Write Cycle:
Load address; wait one cycle; input write data on consecutive K
and K rising edges.
Read Cycle:
Load address; wait one and a half cycle; read data on consec-
utive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
L-H
D(A1) at K(t + 1)
↑
D(A2) at K(t + 1)
↑
L-H
L
H
Q(A1) at C(t + 1)
↑
Q(A2) at C(t + 2)
↑
L-H
H
X
X
X
High-Z
Previous State
High-Z
Previous State
Stopped
Burst Address Table
(CY7C1427AV18, CY7C1418AV18)
First Address (External)
X..X0
X..X1
Second Address (Internal)
X..X1
X..X0
LD#
Vterm = 0.75V
Vterm = 0.75V
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
LD#
C C#
R/W#
ZQ
CQ/CQ#
K#
DQ
A
BUS
MASTER
(CPU
or
ASIC)
SRAM#1
SRAM#2
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
R = 50
ohms
R = 250
ohms
R
= 250ohms
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1418AV18-167BZXI 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418AV18-200BZC 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418AV18-200BZI 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418AV18-200BZXC 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418AV18-200BZXI 36-Mbit DDR-II SRAM 2-Word Burst Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1418AV18-200BZCES 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 36MBIT 2MX18 0.45NS 165FBGA - Bulk
CY7C1418AV18-200BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 DDR II Burst 2 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1418AV18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 DDR II Burst 2 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1418AV18-250BZCES 制造商:Cypress Semiconductor 功能描述:2MX18 DDR-II BURST 2 SRAM - Bulk
CY7C1418AV18-250BZXC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 2Mx18 DDR II Burst 2 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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