參數(shù)資料
型號: CY7C1418AV18-167BZXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 36-Mbit DDR-II SRAM 2-Word Burst Architecture
中文描述: 2M X 18 DDR SRAM, 0.5 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁數(shù): 28/28頁
文件大?。?/td> 456K
代理商: CY7C1418AV18-167BZXC
CY7C1416AV18
CY7C1427AV18
CY7C1418AV18
CY7C1420AV18
Document Number: 38-05616 Rev. *D
Page 28 of 28
Document History Page
Document Title: CY7C1416AV18/CY7C1427AV18/CY7C1418AV18/CY7C1420AV18 36-Mbit DDR-II SRAM 2-Word
Burst Architecture
Document Number: 38-05616
Orig. of
Change
**
247331
See ECN
SYT
New Data Sheet
*A
326519
See ECN
SYT
Removed CY7C1420AV18 from the title
Included 300 MHz Speed grade
Replaced TBDs with their respective values for I
DD
and I
SB1
Added Industrial temperature grade
Replaced the TBDs on the Thermal Characteristics Table to
Θ
JA
= 17.2
°
C/W and
Θ
JC
= 3.2
°
C/W
Replaced TBDs in the Capacitance Table to their respective values for the
165 FBGA Package
Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS
TRI-STATE on Page 18
Added lead-free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per avail-
ability
*B
413953
See ECN
NXR
Converted from preliminary to final
Added CY7C1427AV18 part number to title
Added 278-MHz speed Bin
Changed C, C Description in Feature Section and Pin Description
Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901
North First Street” to “198 Champion Court”
Added Power-up sequence and Wave form on page# 19
Added Footnotes# 13, 14, 15 on page# 19
Replaced Three-state with Tri-state
Changed the description of I
X
from Input Load Current to Input Leakage Current
on page# 20
Modified the I
DD
and I
SB
values
Modified test condition in Footnote #17 on page# 20 from V
DDQ
< V
DD
to V
DDQ
< V
DD
Replaced Package Name column with Package Diagram in the Ordering
Information table.
Updated Ordering Information Table
*C
468029
See ECN
NXR
Modified the ZQ Definition from Alternately, this pin can be connected directly to
V
DD
to Alternately, this pin can be connected directly to V
DDQ
Included Maximum Ratings for Supply Voltage on V
DDQ
Relative to GND
Changed the Maximum Ratings for DC Input Voltage from V
DDQ
to V
DD
Changed t
TH
and t
TL
from 40 ns to 20 ns, changed t
TMSS
, t
TDIS
, t
CS
, t
TMSH
, t
TDIH
,
t
CH
from
10 ns to 5 ns and changed t
TDOV
from 20 ns to 10 ns in TAP AC Switching
Characteristics table
Modified Power-Up waveform
Changed the Maximum rating of Ambient Temperature with Power Applied from
–10°C to +85°C to –55°C to +125°C
Added additional notes in the AC parameter section
Modified AC Switching Waveform
Corrected the typo In the AC Switching Characteristics Table
Updated the Ordering Information Table
*D
505682
See ECN
VKN
Corrected typo in the Functional Description section for burst counter logic
REV.
ECN No.
Issue Date
Description of Change
[+] Feedback
相關(guān)PDF資料
PDF描述
CY7C1418AV18-167BZXI 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418AV18-200BZC 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418AV18-200BZI 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418AV18-200BZXC 36-Mbit DDR-II SRAM 2-Word Burst Architecture
CY7C1418AV18-200BZXI 36-Mbit DDR-II SRAM 2-Word Burst Architecture
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參數(shù)描述
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CY7C1418AV18-250BZC 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1418AV18-250BZCES 制造商:Cypress Semiconductor 功能描述:2MX18 DDR-II BURST 2 SRAM - Bulk
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