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| 型號： | CY7C1416BV18-300BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 4M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 1132K |
| 代理商： | CY7C1416BV18-300BZC |
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PRELIMINARY
CY7C1416BV18
CY7C1427BV18
CY7C1418BV18
CY7C1420BV18
Document Number: 001-07033 Rev. *B
Page 22 of 28
Switching Characteristics
Over the Operating Range
[21, 22]
Cypress
Parameter
t
POWER
Consortium
Parameter
Description
V
DD
(Typical) to the first
Access
[23]
K Clock and C Clock
Cycle Time
Input Clock (K/K and
C/C) HIGH
Input Clock (K/K and
C/C) LOW
K Clock Rise to K Clock
Rise and C to C Rise
(rising edge to rising
edge)
K/K Clock Rise to C/C Clock
Rise
(rising edge to rising edge)
300 MHz
Min.
1
278 MHz
Min. Max. Min. Max. Min. Max. Min. Max.
1
–
1
250 MHz
200 MHz
167 MHz
Unit
ms
Max.
–
1
1
t
CYC
t
KHKH
3.30
5.25
3.6
5.25
4.0
6.3
5.0
7.9
6.0
8.4
ns
t
KH
t
KHKL
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KL
t
KLKH
1.32
–
1.4
–
1.6
–
2.0
–
2.4
–
ns
t
KHKH
t
KHKH
1.49
–
1.6
–
1.8
–
2.2
–
2.7
–
ns
t
KHCH
t
KHCH
0
1.45
0
1.55
0
1.8
0
2.2
0
2.7
ns
Set-up Times
t
SA
t
AVKH
Address Set-up to K
Clock Rise
Control Set-up to K
Clock Rise (LD, R/W)
Double Data Rate
Control Set-up to Clock
(K/K) Rise (BWS
0
,
BWS
1
, BWS
2
, BWS
3
)
D
[X:0]
Set-up to Clock
(K/K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SC
t
IVKH
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
SCDDR
t
IVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
SD[24]
t
DVKH
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
t
HA
t
KHAX
Address Hold after K
Clock Rise
Control Hold after K
Clock Rise (LD, R/W)
Double Data Rate
Control Hold after Clock
(K and K) Rise (BWS
0
,
BWS
1
, BWS
2
, BWS
3
)
D
[X:0]
Hold after Clock
(K and K) Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HC
t
KHIX
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
t
HCDDR
t
KHIX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
t
HD
t
KHDX
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Output Times
t
CO
t
CHQV
C/C Clock Rise (or K/K in
single clock mode) to Data
Valid
Data Output Hold after
Output C/C Clock Rise
(Active to Active)
C/C Clock Rise to Echo
Clock Valid
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
t
DOH
t
CHQX
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
t
CCQO
t
CHCQV
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
Notes:
22.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
23.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a read or write operation
can be initiated.
24.For DQ2 data signal on CY7C1427BV18 device, t
SD
is 0.5ns for 200MHz, 250MHz, 278MHz and 300MHz frequencies.
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1416BV18-300BZI | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1416BV18-300BZXC | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1416BV18-300BZXI | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18 | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18-167BZC | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1418AV18-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418AV18-167BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 36MBIT 2MX18 0.5NS 165FBGA - Bulk |
| CY7C1418AV18-167BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418AV18-200BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 36MBIT 2MX18 0.45NS 165FBGA - Bulk |
| CY7C1418AV18-200BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機(jī)存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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