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參數(shù)資料
| 型號： | CY7C1416BV18-300BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| 中文描述： | 4M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 1132K |
| 代理商： | CY7C1416BV18-300BZC |
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PRELIMINARY
CY7C1416BV18
CY7C1427BV18
CY7C1418BV18
CY7C1420BV18
Document Number: 001-07033 Rev. *B
Page 17 of 28
Identification Register Definitions
Instruction
Field
Revision
Number (31:29)
Cypress Device
ID (28:12)
Cypress JEDEC
ID (11:1)
Value
Description
Version number.
CY7C1416BV18
001
CY7C1420BV18
001
CY7C1427BV18
001
CY7C1418BV18
001
11010100010000111
11010100010001111
11010100010010111 11010100010100111 Defines the type
of SRAM.
Allows unique
identification of
SRAM vendor.
Indicate the
presence of an
ID register.
00000110100
00000110100
00000110100
00000110100
ID Register
Presence (0)
1
1
1
1
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Bit Size
3
1
32
109
Instruction Codes
Instruction
EXTEST
IDCODE
Code
000
001
Description
Captures the Input/Output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1416BV18-300BZI | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1416BV18-300BZXC | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1416BV18-300BZXI | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18 | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
| CY7C1418BV18-167BZC | 36-Mbit DDR-II SRAM 2-Word Burst Architecture |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1418AV18-167BZC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418AV18-167BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 36MBIT 2MX18 0.5NS 165FBGA - Bulk |
| CY7C1418AV18-167BZXC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1418AV18-200BZCES | 制造商:Cypress Semiconductor 功能描述:SRAM SYNC SGL 1.8V 36MBIT 2MX18 0.45NS 165FBGA - Bulk |
| CY7C1418AV18-200BZXC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 DDR II Burst 2 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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