參數(shù)資料
型號(hào): CY7C1394BV18-278BZI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
中文描述: 512K X 36 DDR SRAM, 0.45 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 23/27頁
文件大?。?/td> 446K
代理商: CY7C1394BV18-278BZI
CY7C1392BV18
CY7C1992BV18
CY7C1393BV18
CY7C1394BV18
Document Number: 38-05623 Rev. *C
Page 23 of 27
Switching Waveforms
[28, 29, 30]
Notes:
28.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.
29.Output are disabled (High-Z) one clock cycle after a NOP.
30.In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram
K
1
2
3
4
5
6
7
8
K
LD
R/W
A
Q
D
C
C#
READ
(burst of 2)
READ
(burst of 2)
READ
(burst of 2)
WRITE
(burst of 2)
WRITE
(burst of 2)
tKHCH
tKHCH
NOP
NOP
CQ
CQ#
tKH
tKHKH
tCO
tKL
tCYC
t
tHC
tSA
tHA
tSD
tHD
tSD
tHD
tCLZ
tDOH
SC
tKH
tKHKH
tKL
tCYC
tCQD
tCCQO
tCQOH
tCCQO
tCQOH
DON’T CARE
UNDEFINED
A0
A1
A2
A3
A4
D20
D21
D30
D31
Q40
Q11
Q10
Q41
Q00
Q01
tCQDOH
tCHZ
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相關(guān)PDF資料
PDF描述
CY7C1394BV18-278BZXC 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1394BV18-278BZXI 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1394BV18-300BZC 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1394BV18-300BZI 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
CY7C1394BV18-300BZXC 18-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
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