參數(shù)資料
型號: CY7C1382CV25-225BGI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 512K x 36/1M x 18 Pipelined SRAM
中文描述: 1M X 18 CACHE SRAM, 2.8 ns, PBGA119
封裝: 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件頁數(shù): 11/33頁
文件大小: 537K
代理商: CY7C1382CV25-225BGI
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Document #: 38-05240 Rev. *A
Page 11 of 33
Notes:
5.
The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW
.
Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a
don't care
for the remainder of the write cycle.
OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive or
when the device is deselected, and DQ = data when OE is active.
6.
Write Cycle Descriptions
[1, 5, 6]
Function (1380CV25)
GW
BWE
BWd
BWc
BWb
BWa
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0
DQa
1
0
1
1
1
0
Write Byte 1
DQb
1
0
1
1
0
1
Write Bytes 1, 0
1
0
1
1
0
0
Write Byte 2
DQc
1
0
1
0
1
1
Write Bytes 2, 0
1
0
1
0
1
0
Write Bytes 2, 1
1
0
1
0
0
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3
DQd
1
0
0
1
1
1
Write Bytes 3, 0
1
0
0
1
1
0
Write Bytes 3, 1
1
0
0
1
0
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
0
0
0
1
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Function (1382CV25)
GW
BWE
BWb
BWa
Read
1
1
X
X
Read
1
0
1
1
Write Byte 0
DQ
[7:0]
and DP
0
1
0
1
0
Write Byte 1
DQ
[15:8]
and DP
1
1
0
0
1
Write All Bytes
1
0
0
0
Write All Bytes
0
X
X
X
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