參數(shù)資料
型號: CY7C1382CV25-200BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 512K x 36/1M x 18 Pipelined SRAM
中文描述: 1M X 18 CACHE SRAM, 3 ns, PBGA165
封裝: 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
文件頁數(shù): 18/33頁
文件大?。?/td> 537K
代理商: CY7C1382CV25-200BZC
CY7C1380CV25
CY7C1382CV25
PRELIMINARY
Document #: 38-05240 Rev. *A
Page 18 of 33
Identification Register Definitions
Instruction Field
Revision Number
(31:28)
Cypress Device ID
(27:24)
Device Type
(23:18)
Device Width and Density
(17:12)
Cypress JEDEC ID
(11:0)
512K x 36
0100
1M x 18
0100
Description
Reserved for version number
1011
1011
Reserved for internal use
000000
000000
Defines memory type and architecture
100101
010101
Defines width and density
000001101001
000001101001
Allows unique identification of SRAM
vendor
Scan Register Sizes
Register Name
Bit Size (x18)
Bit Size (x36)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan
51
70
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register be-
tween TDI and TDO. This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register be-
tween TDI and TDO. Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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