參數(shù)資料
型號(hào): CY7C1380C
廠商: Cypress Semiconductor Corp.
英文描述: 18-Mb (512K x 36/1M x 18) Pipelined SRAM
中文描述: 18 MB的(為512k × 36/1M × 18)流水線的SRAM
文件頁數(shù): 25/36頁
文件大?。?/td> 788K
代理商: CY7C1380C
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D
Page 25 of 36
I
SB3
Automatic CE
Power-down
Current—CMOS Inputs
V
DD
= Max, Device Deselected, or
V
IN
0.3V or V
IN
> V
DDQ
– 0.3V
f = f
MAX
= 1/t
CYC
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
7.5-ns cycle, 133 MHz
All speeds
105
100
95
85
80
80
mA
mA
mA
mA
mA
mA
I
SB4
Automatic CE
Power-down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
, f = 0
Shaded areas contain advance information.
Notes:
12.Overshoot: V
(AC) < V
+1.5V (Pulse width less than t
/2), undershoot: V
(AC) > -2V (Pulse width less than t
CYC
/2).
13.TPower-up: Assumes a linear ramp from 0v to V
DD
(min.) within 200ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD\
Thermal Resistance
[14]
Parameter
Θ
JA
Description
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedence, per EIA / JESD51.
TQFP
Package
31
BGA
Package
45
fBGA
Package
46
Unit
°
C/W
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Θ
JC
6
7
3
°
C/W
Capacitance
[14]
Parameter
Description
Test Conditions
TQFP
Package
BGA
Package
fBGA
Package
Unit
C
IN
Input Capacitance
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 3.3V.
V
DDQ
= 2.5V
5
8
9
pF
C
CLK
Clock Input Capacitance
5
8
9
pF
C
I/O
Input/Output Capacitance
5
8
9
pF
Notes:
14.Tested initially and after any design or process change that may affect these parameters
Electrical Characteristics
Over the Operating Range
[12, 13]
(continued)
Parameter
Description
Test Conditions
Min.
Max.
Unit
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