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參數(shù)資料
| 型號(hào)： | CY7C1380C |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| 中文描述： | 18 MB的（為512k × 36/1M × 18）流水線的SRAM |
| 文件頁數(shù)： | 17/36頁 |
| 文件大小： | 788K |
| 代理商： | CY7C1380C |
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CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D
Page 17 of 36
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
TAP AC Switching Characteristics
Over the operating Range
[9, 10]
Parameter
Symbol
Min
Max
Units
Clock
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
Output Times
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Setup Times
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
Hold Times
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
t
TCYC
t
TF
t
TH
t
TL
100
ns
MHz
ns
ns
10
40
40
t
TDOV
t
TDOX
20
ns
ns
0
t
TMSS
t
TDIS
t
CS
10
10
10
ns
ns
t
TMSH
t
TDIH
t
CH
10
10
10
ns
ns
ns
Notes:
9.
CS and
t
CH refer to the setup and hold time requirements of latching data from the boundary scan register.
10.Test conditions are specified using the load in TAP AC test Conditions. t
R
/t
F
= 1ns.
tTL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1380C-167BZC | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1380C-167BZI | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1380D | 18-Mbit (512K x 36/1M x 18) Pipelined SRAM(18-Mb (512K x 36/1M x 18)管道式SRAM) |
| CY7C1381D | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
| CY7C1381D-100AXC | 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1380C-133AC | 功能描述:IC SRAM 18MBIT 133MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1380C-150AC | 制造商:Cypress Semiconductor 功能描述:16MB (512KX36) 3.3V SYNC-PIPE (SINGLE CYCLE DESELECT) SRAM - Bulk |
| CY7C1380C-167AC | 功能描述:IC SRAM 18MBIT 167MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1380C-167BGC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1380C-167BGCT | 制造商:Cypress Semiconductor 功能描述: |
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