參數(shù)資料
型號(hào)： CY7C1380C-200BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 18-Mb (512K x 36/1M x 18) Pipelined SRAM
中文描述： 512K X 36 CACHE SRAM, 3 ns, PBGA119
封裝： 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 788K
代理商： CY7C1380C-200BGC
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D
Page 7 of 36
ADSP
84
A4
B9
Input-
Synchronous
Address Strobe from Processor, sampled
on the rising edge of CLK, active LOW
. When
asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when
CE
1
is deasserted HIGH.
ADSC
85
B4
A8
Input-
Synchronous
Address Strobe from Controller, sampled on
the rising edge of CLK, active LOW
. When
asserted LOW, addresses presented to the
device are captured in the address registers.
A1: A0 are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ
64
T7
H11
Input-
Asynchronous
ZZ “sleep” Input, active HIGH
. When
asserted HIGH places the device in a
non-time-critical “sleep” condition with data
integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
DQs, DQPs
52,53,56,
57,58,59,
62,63,68,
69,72,73,
74,75,78,
79,2,3,6,7,8,9,
12,13,18,19,22
,
23,24,25,
28,29,51,
80,1,30
K6,L6,
M6,N6,
K7,L7,
N7,P7,
E6,F6,
G6,H6,
D7,E7,
G7,H7,
D1,E1,
G1,H1,
E2,F2,
G2,H2,
K1,L1,
N1,P1,
K2,L2,
M2,N2,
P6,D6,
D2,P2
M11,L11,
K11,J11,
J10,K10,
L10,M10,
D10,E10,
F10,G10,
D11,E11,
F11,G11,
D1,E1,F1,
G1,D2,E2,F2,
G2,J1,
K1,L1,M1,
J2,K2,L2,
M2,N11,
C11,C1,N1
I/O-
Synchronous
Bidirectional Data I/O lines
. As inputs, they
feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs,
they deliver the data contained in the memory
location specified by the addresses presented
during the previous clock rise of the read cycle.
The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQs and DQP
X
are
placed in a tri-state condition.
V
DD
15,41,65,
91
J2,C4,J4,R4,
J6
D4,D8,E4,E8,
F4,F8,
G4,G8,H4,H8,
J4,J8,
K4,K8,L4,
L8,M4,M8
Power Supply
Power supply inputs to the core of the de-
vice
.
V
SS
17,40,67,
90
D3,E3,
F3,H3,
K3,M3,
N3,P3,
D5,E5,
F5,H5,
K5,M5,
N5,P5
C4,C5,C6,C7,
C8,D5,D6,D7,
E5,E6,E7,F5,
F6,F7,G5,G6,
G7,H2,H5,H6,
H7,J5,J6,J7,
K5,K6,K7,
L5,L6,L7,
M5,M6,M7,N4,
N8
Ground
Ground for the core of the device
.
CY7C1380C–Pin Definitions
(continued)
Name
TQFP
BGA
fBGA
I/O
Description
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