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| 型號(hào)： | CY7C1380C-200BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| 中文描述： | 512K X 36 CACHE SRAM, 3 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 14/36頁 |
| 文件大?。?/td> | 788K |
| 代理商： | CY7C1380C-200BGC |
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CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D
Page 14 of 36
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle,Suspend Burst
WRITE Cycle,Suspend Burst
Next
Next
Next
Current
Current
Current
Current
Current
Current
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
L
L
H
H
H
H
L
L
H
X
X
L
H
L
H
X
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Tri-State
D
D
Q
Tri-State
Q
Tri-State
D
D
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CE
1
, CE
2
, and CE
3
are available only in the TQFP package. BGA package has only 2 chip selects CE
1
and CE
2
.
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Truth Table for Read/Write
[5]
Function (CY7C1380C)
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
BW
D
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BW
C
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
X
BW
B
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
X
BW
A
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
X
Read
Read
Write Byte A – ( DQ
A
and DQP
A
)
Write Byte B – ( DQ
B
and DQP
B
)
Write Bytes B, A
Write Byte C – ( DQ
C
and DQP
C
)
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – ( DQ
D
and DQP
D
)
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
Write All Bytes
Truth Table for Read/Write
[5]
Function (CY7C1382C)
GW
H
H
H
H
H
H
L
BWE
H
L
L
L
L
L
X
BW
B
X
H
H
L
L
L
X
BW
A
X
H
L
H
L
L
X
Read
Read
Write Byte A – ( DQ
A
and DQP
A
)
Write Byte B – ( DQ
B
and DQP
B
)
Write Bytes B, A
Write All Bytes
Write All Bytes
Truth Table
[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
CE
1
CE
2
CE
3
ZZ
ADSP
ADSC
ADV
WRITE
OE CLK
DQ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1380C-250AC | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1380C-250BGC | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1380C-225BGC | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
| CY7C1380C | 18-Mb (512K x 36/1M x 18) Pipelined SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1380C225AC | 制造商:Cypress 功能描述:_ |
| CY7C1380C-225AC | 制造商:Cypress 功能描述:_ 制造商:Cypress Semiconductor 功能描述: |
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| CY7C1380D-133AXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 1CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1380D-133AXCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 512Kx36 3.3V COM 1CD Sync PL 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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