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參數(shù)資料
| 型號： | CY7C1372C-250BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture |
| 中文描述： | 1M X 18 ZBT SRAM, 2.6 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 19/27頁 |
| 文件大?。?/td> | 704K |
| 代理商： | CY7C1372C-250BZC |
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CY7C1370C
CY7C1372C
Document #: 38-05233 Rev. *D
Page 19 of 27
Capacitance
[16]
Switching Characteristics
Over the Operating Range
[ 21, 22]
Parameter
C
IN
C
CLK
C
I/O
Description
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
DD
= 2.5V V
DDQ
= 2.5V
BGA Max.
8
8
8
fBGA Max.
9
9
9
TQFP Max.
5
5
5
Unit
pF
pF
pF
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Thermal Resistance
[16]
Parameters
Q
JA
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance, per EIA
/ JESD51.
BGA Typ.
45
fBGA Typ.
46
TQFP Typ.
31
Unit
°
C/W
Notes
17
Q
JC
7
3
6
°
C/W
17
Output
R=1667
R = 1538
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R
L
= 50
Z
0
= 50
V
L
= 1.25V
2.5V
ALL INPUT PULSES
[16]
V
DD
0V
90%
10%
90%
10%
< 1.0 ns
< 1.0 ns
(c)
AC Test Loads and Waveforms
1.25V
Parameter
t
Power[17]
Clock
t
CYC
F
MAX
t
CH
t
CL
Output Times
t
CO
t
EOV
t
DOH
t
CHZ
t
CLZ
t
EOHZ
t
EOLZ
Shaded areas contain advance information.
Notes:
16.Tested initially and after any design or process changes that may affect these parameters.
17.This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can be
initiated.
18.t
, t
, t
, and t
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
19.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20.This parameter is sampled and not 100% tested.
21.Timing reference is 1.5V when V
3.3V and is 1.25V when V
2.5V.
22.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Description
-250
-225
-200
-167
Unit
ms
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
Min.
1
Max.
V
CC
(typical) to the first access read or write
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
Clock LOW
4.0
4.4
5
6
ns
MHz
ns
ns
250
225
200
166
1.7
1.7
2.0
2.0
2.0
2.0
2.2
2.2
Data Output Valid After CLK Rise
OE LOW to Output Valid
Data Output Hold After CLK Rise
Clock to High-Z
[18, 19, 20]
Clock to Low-Z
[18, 19, 20]
OE HIGH to Output High-Z
[18, 19, 20]
OE LOW to Output Low-Z
[18, 19, 20]
2.6
2.6
2.8
2.8
3.0
3.0
3.4
3.4
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
1.3
1.3
2.6
2.8
3.0
3.4
1.0
1.0
1.3
1.3
2.6
2.8
3.0
3.4
0
0
0
0
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| CY7C1372CV25-167BZC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1372D-167AXC | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 3.3V NoBL Sync PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1372D-167AXCT | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 3.3V NoBL Sync PL 靜態(tài)隨機存取存儲器 COM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1372D-167AXI | 功能描述:靜態(tài)隨機存取存儲器 1Mx18 3.3V NoBL Sync PL 靜態(tài)隨機存取存儲器 IND RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1372D-167AXIKJ | 制造商:Cypress Semiconductor 功能描述: |
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