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參數(shù)資料
| 型號(hào)： | CY7C1370C-200BZC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture |
| 中文描述： | 512K X 36 ZBT SRAM, 3 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165 |
| 文件頁數(shù)： | 21/27頁 |
| 文件大小： | 704K |
| 代理商： | CY7C1370C-200BZC |
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CY7C1370C
CY7C1372C
Document #: 38-05233 Rev. *D
Page 21 of 27
Notes:
26.The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
27.Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
28.I/Os are in High-Z when exiting ZZ sleep mode.
Switching Waveforms
(continued)
NOP,STALL AND DESELECT CYCLES
[23,24,26]
READ
Q(A3)
4
5
6
7
8
9
10
CLK
CE
WE
CEN
BWx
ADV/LD
ADDRESS
A3
A4
A5
D(A4)
Data
In-Out (DQ)
A1
Q(A5)
WRITE
D(A4)
STALL
WRITE
D(A1)
1
2
3
READ
Q(A2)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
t
CHZ
A2
D(A1)
Q(A2)
Q(A3)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
ZZ
Mode Timing
[27,28]
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