參數(shù)資料
型號(hào)： CY7C1370C-200BZC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
中文描述： 512K X 36 ZBT SRAM, 3 ns, PBGA165
封裝： 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165
文件頁(yè)數(shù)： 15/27頁(yè)
文件大?。?/td> 704K
代理商： CY7C1370C-200BZC
CY7C1370C
CY7C1372C
Document #: 38-05233 Rev. *D
Page 15 of 27
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
CY7C1370C
010
01010001000100101
00000110100
1
CY7C1372C
010
01010001000010101 Reserved for future use.
00000110100
Allows unique identification of SRAM vendor.
1
Indicate the presence of an ID register.
Description
Reserved for version number.
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Bit Size(x18)
3
1
32
70
Bit Size (x36)
3
1
32
70
Identification Codes
Instruction
EXTEST
Code
000
Description
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO.
Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function
and is therefore not 1149.1-compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
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