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參數(shù)資料
| 型號： | CY7C1365V25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 512K x 18 Flowthrough SRAM(512K x 18 流通式 SRAM) |
| 中文描述： | 直通為512k × 18的SRAM（為512k × 18流通式的SRAM） |
| 文件頁數(shù)： | 1/30頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CY7C1365V25 |
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PRELIMINARY
256K x 36/256K x 32/512K x 18 Flowthrough SRAM
CY7C1361V25
CY7C1363V25
CY7C1365V25
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
December 1, 1999
408-943-2600
Features
Supports 113-MHz bus operations
256K x 36 / 256K x 32 / 512K x 18 common I/O
Fast clock-to-output times
—7.5 ns (for 117-MHz device)
—8.5 ns (for 100-MHz device)
—10.0 ns (for 80-MHz device)
Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequences
Separate processor and controller address strobes
provide direct interface with the processor and external
cache controller
Synchronous self-timed writes
Asynchronous output enable
Single 2.5V Power supply
JEDEC-standard pinout
Available as a 100-pin TQFP or 119 BGA
“ZZ” Sleep Mode option
Functional Description
The CY7C1361V25, CY7C1365V25 and CY7C1363V25 are
2.5v, 256K x 36, 256K x 32 and 512K x 18 synchronous-
flowthrough SRAM designed to interface with high-speed mi-
croprocessors with minimal glue logic. Maximum access delay
from the clock rise is 7.5 ns (117-MHz device). A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the
rest of the burst access.
The CY7C1361V25/CY7C1365V25/CY7C1363V25 supports
either the interleaved or linear burst sequences, selected by
the MODE input pin. A HIGH selects an interleaved burst se-
quence, while a LOW selects a linear burst sequence. Burst
accesses can be initiated by asserting either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC) at clock rise. Address advancement through the burst
sequence is controlled by the ADV input. Byte write operations
are qualified with the Byte Write Select (BW
a,b,c,d
for
CY7C1361V25/CY7C1365V25 and BW
a,b
for CY7C1363V25)
inputs. A Global Write Enable (GW) overrides all byte write
inputs and writes data to all four bytes. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank selec-
tion and output three-state control.
CLK
A
x
GW
CE
1
CE
BWE
BW
x
MODE
ADSP
ADSC
CE
2
OE
256Kx36/
512Kx18
MEMORY
ARRAY
Logic Block Diagram
DQ
x
DP
x
Data-In REG.
Q
CE
CONTROL
and WRITE
LOGIC
3
ADV
7C1361/65
A
[17:0]
DQ
a,b,c,d
DP
a,b,c,d
BW
a,b,c,d
7C1363
A
[18:0]
DQ
a,b,c,d
DP
a,b
BW
a,b
A
X
DQ
X
DP
X
BW
X
ZZ
Selection Guide
7C1361-133
7C1365-133
7C1363-133
7C1361-117
7C1365-117
7C1363-117
7C1361-100
7C1365-100
7C1363-100
7C1361-80
7C1365-80
7C1363-80
Maximum Access Time (ns)
6.5
7.5
8.5
10.0
Maximum Operating Current (mA)
Commercial
350
300
260
210
Maximum CMOS Standby Current (mA)
10
10
10
10
Shaded areas contain advance information.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1362V25 | 256K x 32 Pipelined SRAM(256K x 32 流水線式 SRAM) |
| CY7C1360V25 | 256K x 36 Pipelined SRAM(256K x 36 流水線式 SRAM) |
| CY7C1364V25 | 512K x 18 Pipelined SRAM(512K x 18 流水線式 SRAM) |
| CY7C1363B-133BGI | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
| CY7C1361B-100AC | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1366A-166AJC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1366A-166BGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1366A-200AJC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1366B-166BGC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36 3.5ns 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:8M- 256KX36 3.3V PIPELINE 2CD-SYNCHRONOUS SRAM - Bulk |
| CY7C1366C-133BGC | 功能描述:靜態(tài)隨機存取存儲器 256Kx32 3.3V COM Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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