- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378500 > CY7C1361C-133BZXI (CYPRESS SEMICONDUCTOR CORP) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM PDF資料下載
參數(shù)資料
| 型號： | CY7C1361C-133BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM |
| 中文描述： | 256K X 36 CACHE SRAM, 6.5 ns, PBGA165 |
| 封裝： | 15 X 13 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165 |
| 文件頁數(shù)： | 1/31頁 |
| 文件大?。?/td> | 519K |
| 代理商： | CY7C1361C-133BZXI |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
CY7C1361C
CY7C1363C
Cypress Semiconductor Corporation
Document #: 38-05541 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised September 14, 2006
Features
Supports 100, 133-MHz bus operations
Supports 100-MHz bus operations (Automotive)
256K × 36/512K × 18 common I/O
3.3V –5% and +10% core power supply (V
DD
)
2.5V or 3.3V I/O power supply (V
DDQ
)
Fast clock-to-output times
— 6.5 ns (133-MHz version)
Provide high-performance 2-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
Available in lead-free 100-Pin TQFP package, lead-free
and non lead-free 119-Ball BGA package and 165-Ball
FBGA package
TQFP Available with 3-Chip Enable and 2-Chip Enable
IEEE 1149.1 JTAG-Compatible Boundary Scan
“ZZ” Sleep Mode option
Functional Description
[1]
The CY7C1361C/CY7C1363C is a 3.3V, 256K x 36/512K x 18
Synchronous Flow-through SRAMs, respectively designed to
interface with high-speed microprocessors with minimum glue
logic. Maximum access delay from clock rise is 6.5 ns
(133-MHz version). A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
1
), depth-expansion Chip Enables (CE
2
and CE
3[2]
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW
x
,
and BWE), and Global Write (GW). Asynchronous inputs
include the Output Enable (OE) and the ZZ pin.
The CY7C1361C/CY7C1363C allows either interleaved or
linear burst sequences, selected by the MODE input pin. A
HIGH selects an interleaved burst sequence, while a LOW
selects a linear burst sequence. Burst accesses can be
initiated with the Processor Address Strobe (ADSP) or the
cache Controller Address Strobe (ADSC) inputs. Address
advancement is controlled by the Address Advancement
(ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
The CY7C1361C/CY7C1363C operates from a +3.3V core
power supply while all outputs may operate with either a +2.5
or +3.3V supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
133 MHz
6.5
250
40
100 MHz
8.5
180
40
60
Unit
ns
mA
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Comm/Ind’l
Automotive
Notes:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
2. CE
3
is for A version of TQFP (3 Chip Enable Option) and 165 FBGA package only. 119 BGA is offered only in 2 Chip Enable.
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1361V25 | 256K x 36 Flowthrough SRAM(256K x 36 流通式 SRAM) |
| CY7C1363V25 | 256K x 32 Flowthrough SRAM(256K x 32 流通式 SRAM) |
| CY7C1365V25 | 512K x 18 Flowthrough SRAM(512K x 18 流通式 SRAM) |
| CY7C1362V25 | 256K x 32 Pipelined SRAM(256K x 32 流水線式 SRAM) |
| CY7C1360V25 | 256K x 36 Pipelined SRAM(256K x 36 流水線式 SRAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1361S-100AXC | 功能描述:IC SRAM 256KX36 3.3V SYN 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C1361S-133AXC | 功能描述:靜態(tài)隨機存取存儲器 CY7C1361S-133AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1361S-133AXCT | 功能描述:靜態(tài)隨機存取存儲器 CY7C1361S-133AXCT RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1361S-133AXI | 功能描述:IC SRAM 256KX36 3.3V SYN 100TQFP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| CY7C1361S-133AXIT | 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。