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參數(shù)資料
| 型號： | CY7C1359A-133AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 中文描述： | 256K X 18 CACHE TAG SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大小： | 244K |
| 代理商： | CY7C1359A-133AC |
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 21 of 24
Read/Write Timing without Burst Feature
[32, 34, 35]
Notes:
34. In this timing diagram, it is assumed that burst feature is not used and therefore ADSP is tied to HIGH (V
CC
) and ADSC is tied to LOW (V
SS
). The logic state
of ADV is a
“
Don
’
t Care
”
.
35. In this timing diagram, it is assumed that WE = [BWE + WEL*WEH]*GW.
Switching Waveforms
(continued)
CLK
ADDRESS
WE#
CE#
DEN#
OE#
DQ
A1
A2
A4
Q(A1)
Q(A2)
t
S
t
H
t
KC
A5
D(A5)
D(A6)
Reads
A8
A3
A6
A7
Q(A3)
Q(A4)
D(A7)
D(A8)
t
KH
t
KL
t
KQ
t
KQX
t
OEHZ
t
OEQ
t
OELZ
t
KQLZ
t
KQHZ
Writes
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| CY7C1359A-150AC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 4M-Bit 256K x 16 3.8ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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