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參數(shù)資料
| 型號(hào)： | CY7C1359A-133AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 中文描述： | 256K X 18 CACHE TAG SRAM, 4 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 244K |
| 代理商： | CY7C1359A-133AC |
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 16 of 24
AC Test Loads and Waveforms
(a)
ALL INPUT PULSES
2.5V
0V
90%
10%
90%
10%
≤
1.8 ns
≤
1.8 ns
(c)
(b)
Vt = 1.25V
30 pF
DQ
Z
0
= 50
50
DQ
+2.5v
1,667
1,538
5 pF
(b)
Switching Characteristics
Over the Operating Range
[27]
-6
166 MHz
Min.
-6.7
150 MHz
Min.
-7.5
133 MHz
Min.
-10
100 MHz
Min.
Parameter
Clock
t
KC
t
KF
t
KH
t
KL
Output Times
t
KQ
t
KM
t
KQX
t
KMX
t
KQLZ
t
KQHZ
t
OEQ
t
MOEM
t
OELZ
t
MOELZ
t
OEHZ
t
MOEHZ
Set-up Times
t
S
Hold Times
t
H
Notes:
27. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
28. Output loading is specified with C
= 5 pF as in AC Test Loads.
29. At any given temperature and voltage condition, t
is less than t
, t
is less than t
and t
is less than t
.
30. OE is a
“
Don
’
t Care
”
after a write cycle begins To prevent bus contention, OE should be negated prior before the start of write cycle.
31. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for
“
don
’
t care
”
as defined in the truth table.
Description
Max.
Max.
Max.
Max.
Unit
Clock Cycle Time
6.0
6.7
7.5
8.5
ns
Clock Frequency
Clock HIGH Time
2.4
2.4
2.6
2.6
2.8
2.8
3.4
3.4
ns
ns
Clock LOW Time
Clock to Output Valid
Clock to MATCH Valid
Clock to Output Invalid
Clock to MATCH Invalid
Clock to Output in Low-Z
[17, 28, 29]
Clock to Output in High-Z
[17, 28, 29]
OE to Output Valid
[30]
MOE to MATCH Valid
[30]
OE to Output in Low-Z
[17, 28, 29]
MOE to MATCH in Low-Z
[17, 28, 29]
OE to Output in High-Z
[17, 28, 29]
MOE to MATCH in High-Z
[17, 28, 29]
3.5
3.8
4.0
4.0
ns
1.5
1.5
1.5
1.5
ns
0
0
0
0
ns
ns
ns
1.5
6.0
3.5
1.5
6.7
3.5
1.5
7.5
3.8
1.5
8.5
3.8
0
0
0
0
ns
3.5
3.5
3.8
3.8
ns
Address, Controls, and Data In
[31]
1.5
1.5
1.5
2.0
ns
Address, Controls, and Data In
[31]
0.5
0.5
0.5
0.5
ns
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