參數(shù)資料
型號(hào): CY7C1356CV25-166BZC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
中文描述: 512K X 18 ZBT SRAM, 3.5 ns, PBGA165
封裝: 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
文件頁數(shù): 12/28頁
文件大?。?/td> 444K
代理商: CY7C1356CV25-166BZC
CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *H
Page 12 of 28
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
[11, 12]
Parameter
Clock
t
TCYC
t
TF
t
TH
t
TL
Output Times
t
TDOV
t
TDOX
Set-up Times
t
TMSS
t
TDIS
t
CS
Hold Times
t
TMSH
t
TDIH
t
CH
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH Time
TCK Clock LOW Time
50
ns
MHz
ns
ns
20
20
20
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
10
ns
ns
0
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
5
5
5
ns
ns
ns
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
5
5
5
ns
ns
ns
Notes:
11. t
and t
refer to the set-up and hold time requirements of latching data from the boundary scan register.
12.Test conditions are specified using the load in TAP AC test Conditions. t
R
/t
F
= 1 ns.
tTL
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTH
Test Data-Out
(TDO)
tCYC
Test Data-In
(TDI)
tTMSH
tTMSS
tTDIH
tTDIS
tTDOX
tTDOV
DON’T CARE
UNDEFINED
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相關(guān)PDF資料
PDF描述
CY7C1356CV25-166BZI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1356CV25-166BZXC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1356CV25-166BZXI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1356CV25-200AXC 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
CY7C1356CV25-200AXI 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL⑩ Architecture
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