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| 型號(hào)： | CY7C1352B-166AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 256K x 18 Pipilined SRAm with NoBL Architecture |
| 中文描述： | 256K X 18 ZBT SRAM, 3.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 189K |
| 代理商： | CY7C1352B-166AC |
CY7C1352B
PRELIMINARY
8
Switching Characteristics
Over the Operating Range
[11, 12, 13]
-166
-150
-143
-133
-100
-80
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
CYC
t
CH
t
CL
t
AS
Clock Cycle Time
5.0
6.6
7.0
7.5
10
12.5
ns
Clock HIGH
1.4
2.5
2.8
3.0
4.0
4.0
ns
Clock LOW
1.4
2.5
2.8
3.0
4.0
4.0
ns
Address Set-Up Before CLK
Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
t
AH
t
CO
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
Data Output Valid After CLK
Rise
3.5
3.8
4.0
4.2
5.0
7.0
ns
t
DOH
Data Output Hold After CLK
Rise
1.5
1.5
1.5
1.5
1.5
1.5
ns
t
CENS
t
CENH
t
WES
CEN Set-Up Before CLK Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
CEN Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
GW, BWS
[1:0]
Set-Up Before
CLK Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
t
WEH
GW, BWS
[1:0]
Hold After CLK
Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
t
ALS
ADV/LD Set-Up Before CLK
Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
t
ALH
t
DS
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
Data Input Set-Up Before
CLK Rise
1.5
1.5
1.7
1.7
2.0
2.5
ns
t
DH
Data Input Hold After CLK
Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
t
CES
Chip Enable Set-Up Before
CLK Rise
1.5
1.5
2.0
2.0
2.2
2.5
ns
t
CEH
Chip Enable Hold After CLK
Rise
Clock to High-Z
[10, 12, 13, 14]
Clock to Low-Z
[10, 12, 13, 14]
OE HIGH to Output High-Z
[10,
12, 13, 14]
0.5
0.5
0.5
0.5
0.5
1.0
ns
t
CHZ
t
CLZ
t
EOHZ
1.5
3.2
1.5
3.2
1.5
3.5
1.5
3.5
1.5
3.5
1.5
5.0
ns
1.5
1.5
1.5
1.5
1.5
1.5
ns
3.0
3.0
4.0
4.2
5.0
7.0
ns
t
EOLZ
OE LOW to Output Low-Z
[10,
12, 13, 14]
0
0
0
0
0
0
ns
t
EOV
OE LOW to Output Valid
[12]
3.2
3.5
4.0
4.2
5.0
7.0
ns
Shaded areas contain advance information.
Notes:
12. t
, t
, t
, t
, and t
EOHZ
are specified with A/C test conditions shown in part (a) of AC Test Loads and waveforms. Transition is measured
±
200 mV
from steady-state voltage.
13. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
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