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參數(shù)資料
| 型號(hào)： | CY7C1345 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 128K x 36 Synchronous Flow-Through 3.3V Cache RAM(3.3V 128K x 36 同步流通式高速緩沖RAM) |
| 中文描述： | 128K的× 36同步流動(dòng)，通過(guò)3.3V的高速緩存內(nèi)存（3.3 128K的× 36同步流通式高速緩沖內(nèi)存） |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大?。?/td> | 273K |
| 代理商： | CY7C1345 |
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128K x 36 Synchronous Flow-Through 3.3V Cache RAM
Functional Description
CY7C1345
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 2, 1999
Features
Supports 117-MHz microprocessor cache systems with
zero wait states
128K by 36 common I/O
Fast clock-to-output times
—7.5 ns (117-MHz version)
Two-bit wrap-around counter supporting either
interleaved or linear burst sequence
Separate processor and controller address strobes pro-
vide direct interface with the processor and external
cache controller
Synchronous self-timed write
Asynchronous output enable
3.3V I/Os
JEDEC-standard pinout
100-pin TQFP packaging
ZZ “sleep” mode
The CY7C1345 is a 3.3V, 128K by 36 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1345 allows either interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs. Address advancement is controlled by the ad-
dress advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Selection Guide
7C1345–117
7C1345–100
7C1345–90
7C1345–50
Maximum Access Time (ns)
7.5
8.0
8.5
11.0
Maximum Operating Current (mA)
350
325
300
250
Maximum Standby Current (mA)
2.0
2.0
2.0
2.0
Pentium is a registered trademark of Intel Corporation.
CLK
ADV
ADSC
ADSP
A
[16:0]
GW
BWE
BWS
3
BWS
0
1
CE
2
CE
3
OE
ZZ
BURST
COUNTER
DBYTEWRITE
REGISTERS
ADDRESS
REGISTER
D
Q
INPUT
REGISTERS
CLK
128K X 36
MEMORY
ARRAY
Q
0
Q
1
Q
D
CE
CE
CLR
SLEEP
BYTEWRITE
REGISTERS
D
Q
D
Q
DQ[15:8],DP1
BYTEWRITE
DQ[7:0],DP0
BYTEWRITE
D
Q
ENABLE
REGISTER
CLK
D
Q
36
36
17
15
15
17
(A
0
,A
1
)
2
MODE
Logic Block Diagram
DQ
[31:0]
DP
[3:0]
BWS
1
BWS
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1346H | 2-Mbit (64K x 36) Pipelined Sync SRAM |
| CY7C1346H-166AXC | 2-Mbit (64K x 36) Pipelined Sync SRAM |
| CY7C1346H-166AXI | 2-Mbit (64K x 36) Pipelined Sync SRAM |
| CY7C1346 | 64K x 36 Synchronous-Pipelined Cache RAM(64K x 36同步流水線式高速緩沖存儲(chǔ)器 RAM) |
| CY7C1347B-100AC | 128K x 36 Synchronous-Pipelined Cache RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1345A-100AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1345A-117AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1345B-100AC | 制造商:Cypress Semiconductor 功能描述:Cache Mem 4.5M-Bit 3.3V SRAM 100-Pin TQFP |
| CY7C1345B-100ACT | 制造商:Cypress Semiconductor 功能描述:Cache Mem 4.5M-Bit 3.3V SRAM 100-Pin TQFP T/R |
| CY7C1345B-100AI | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
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