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參數(shù)資料
| 型號： | CY7C1346H |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 2-Mbit (64K x 36) Pipelined Sync SRAM |
| 中文描述： | 2兆位（64K的× 36）流水線同步靜態(tài)存儲器 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 693K |
| 代理商： | CY7C1346H |
2-Mbit (64K x 36) Pipelined Sync SRAM
CY7C1346H
Cypress Semiconductor Corporation
Document #: 38-05672 Rev. *B
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 26, 2006
Features
Registered inputs and outputs for pipelined operation
64K × 36 common I/O architecture
3.3V core power supply
3.3V/2.5V I/O operation
Fast clock-to-output times
— 3.5 ns (166-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Offered in JEDEC-standard lead-free 100-pin TQFP
package
“ZZ” Sleep Mode Option
Functional Description
[1]
The CY7C1346H SRAM integrates 64K x 36 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
2
and
CE
), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the Byte Write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1346H operates from a +3.3V core power supply
while all outputs also operate with either a +3.3V/2.5V supply.
All
inputs
and
outputs
JESD8-5-compatible.
are
JEDEC-standard
Note:
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on www.cypress.com.
Logic Block Diagram
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER
AND
LOGIC
CLR
Q1
Q0
ADSP
ADSC
MODE
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
OUTPUT
REGISTERS
SENSE
OUTPUT
BUFFERS
E
PIPELINED
ENABLE
INPUT
REGISTERS
A0, A1, A
BW
B
BW
C
BW
D
BW
A
ARRAY
SLEEP
CONTROL
ZZ
A
[1:0]
2
DQ
A
,DQP
A
BYTE
WRITE REGISTER
DQ
B,
DQP
B
BYTE
WRITE REGISTER
DQ
C
,DQP
C
BYTE
WRITE REGISTER
DQ
D,
DQ
D
BYTE
WRITE REGISTER
DQ
A,
DQP
A
BYTE
WRITE DRIVER
DQ
B,
DQP
B
BYTE
WRITE DRIVER
DQ
C
,DQP
C
BYTE
WRITE DRIVER
DQ
D
,DQP
D
BYTE
WRITE DRIVER
DQP
A
DQP
B
DQP
C
DQP
D
DQs
[+] Feedback
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| CY7C1346H-166AXC | 功能描述:靜態(tài)隨機存取存儲器 64X36 2M PL 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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| CY7C1347A-117AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
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