參數(shù)資料
型號: CY7C1339
廠商: Cypress Semiconductor Corp.
英文描述: 128K x 32 Synchronous-Pipelined Cache RAM(128K x 32 同步流水線式高速緩沖存儲器 RAM)
中文描述: 128K的× 32同步流水線緩存內(nèi)存(128K的× 32同步流水線式高速緩沖存儲器的RAM)
文件頁數(shù): 1/15頁
文件大?。?/td> 277K
代理商: CY7C1339
128K x 32 Synchronous-Pipelined Cache RAM
The CY7C1339 I/O pins can operate at either the 2.5V or the
3.3V level; the I/O pins are 3.3V tolerant when V
DDQ
=2.5V.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1339 supports either the interleaved burst se-
quence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The burst
sequence is selected through the MODE pin. Accesses can
be initiated by asserting either the Processor Address Strobe
(ADSP) or the Controller Address Strobe (ADSC) at clock rise.
Address advancement through the burst sequence is con-
trolled by the ADV input. A 2-bit on-chip wraparound burst
counter captures the first address in a burst sequence and
automatically increments the address for the rest of the burst
access.
Byte write operations are qualified with the four Byte Write
Select (BW
[3:0]
) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write cir-
cuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to provide prop-
er data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
CY7C1339
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
August 2, 1999
Features
Supports 100-MHz bus for Pentium
operations with zero wait states
Fully registered inputs and outputs for pipelined oper-
ation
128K by 32 common I/O architecture
3.3V core power supply
2.5V / 3.3V I/O operation
Fast clock-to-output times
—3.5 ns (for 166-MHz device)
—4.0 ns (for 133-MHz device)
—5.5 ns (for 100-MHz device)
User-selectable burst counter supporting Intel
tium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100 TQFP pinout
“ZZ” Sleep Mode option and Stop Clock option
and PowerPC
Pen-
Functional Description
The CY7C1339 is a 3.3V, 128K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Intel and Pentium are trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
CLK
ADV
ADSC
ADSP
A
[16:0]
GW
BWE
BW
3
BW
2
BW
1
BW
0
1
CE
2
CE
3
OE
ZZ
BURST
COUNTER
DQ[31:24]
ADDRESS
REGISTER
D
Q
ROUTPUT
CLK
INPUT
REGISTERS
CLK
128KX32
MEMORY
ARRAY
Q
0
Q
1
Q
D
CE
CLR
SLEEP
DQ[23:16]
D
Q
D
Q
DQ[15:8]
BDQ[7:0]
D
Q
ENABLE
REGISTER
CLK
D
CE
Q
ENREGISTER
CLK
D
Q
32
32
17
15
15
17
(A
[1;0]
)
2
MODE
Logic Block Diagram
DQ
[31:0]
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