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參數(shù)資料
| 型號： | CY7C1338G |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 4-Mbit (128K x 32) Flow-Through Sync SRAM(4-Mb (128K x 32)流通式同步SRAM) |
| 中文描述： | 4兆位（128K的× 32）流量，通過同步靜態(tài)存儲器（4字節(jié)（128K的× 32）流通式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 365K |
| 代理商： | CY7C1338G |
CY7C1338G
Document #: 38-05521 Rev. *D
Page 10 of 17
Switching Characteristics
Over the Operating Range
[11, 12, 13, 14, 15, 16]
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
Output Times
t
CDV
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Setup Times
t
AS
t
ADS
t
ADVS
t
WES
t
DS
t
CES
Hold Times
t
AH
t
ADH
t
WEH
t
ADVH
t
DH
t
CEH
Description
–133
–100
Unit
ms
Min.
1
Max.
Min.
1
Max.
V
DD
(Typical) to the first Access
[11]
Clock Cycle Time
Clock HIGH
Clock LOW
7.5
2.5
2.5
10
4.0
4.0
ns
ns
ns
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[12, 13, 14]
Clock to High-Z
[12, 13, 14]
OE LOW to Output Valid
OE LOW to Output Low-Z
[12, 13, 14]
OE HIGH to Output High-Z
[12, 13, 14]
6.5
8.0
ns
ns
ns
ns
ns
ns
ns
2.0
0
2.0
0
3.5
3.5
3.5
3.5
0
0
3.5
3.5
Address Set-up Before CLK Rise
ADSP, ADSC Set-up Before CLK Rise
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
1.5
2.0
ns
ns
ns
ns
ns
ns
ADV Set-up Before CLK Rise
GW, BWE, BW
X
Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-up
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
GW, BWE, BW
X
Hold After CLK Rise
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Notes:
11. This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
12.t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
13.At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14.This parameter is sampled and not 100% tested.
15.Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
16.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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相關代理商/技術參數(shù) |
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| CY7C1338G-100AXC | 功能描述:靜態(tài)隨機存取存儲器 128Kx32 3.3V COM Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1338G-100AXCT | 功能描述:靜態(tài)隨機存取存儲器 128Kx32 3.3V COM Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1338G-117AXC | 功能描述:靜態(tài)隨機存取存儲器 128Kx32 3.3V COM Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1338G-117AXCT | 功能描述:靜態(tài)隨機存取存儲器 128Kx32 3.3V COM Sync FT 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1338S-100AXC | 功能描述:靜態(tài)隨機存取存儲器 CY7C1338S-100AXC RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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