- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380186 > CY7C1305BV25 (Cypress Semiconductor Corp.) 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture(18Mbit，Burst of 4，QDR結(jié)構(gòu)，流水線SRAM) PDF資料下載
參數(shù)資料
| 型號(hào)： | CY7C1305BV25 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit Burst of 4 Pipelined SRAM with QDR Architecture(18Mbit，Burst of 4，QDR結(jié)構(gòu)，流水線SRAM) |
| 中文描述： | 18兆位的4四年防務(wù)審查架構(gòu)（18Mbit，4突發(fā)流水線SRAM的突發(fā)，國(guó)防評(píng)估報(bào)告結(jié)構(gòu)，流水線的SRAM） |
| 文件頁(yè)數(shù)： | 1/21頁(yè) |
| 文件大?。?/td> | 884K |
| 代理商： | CY7C1305BV25 |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)
18-Mbit Burst of 4 Pipelined SRAM with
QDR Architecture
CY7C1307BV25
CY7C1305BV25
Cypress Semiconductor Corporation
Document #: 38-05630 Rev. *A
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 3, 2006
Features
Separate independent Read and Write data ports
Supports concurrent transactions
167-MHz clock for high bandwidth
2.5 ns Clock-to-Valid access time
4-Word Burst for reducing the address bus frequency
Double Data Rate (DDR) interfaces on both Read and
Write Ports (data transferred at 333 MHz) @167 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
Single multiplexed address input bus latches address
inputs for both Read and Write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
2.5V core power supply with HSTL Inputs and Outputs
Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–1.9V)
JTAG interface
Configurations
CY7C1305BV25 – 1M x 18
CY7C1307BV25 – 512K x 36
Functional Description
The CY7C1305BV25/CY7C1307BV25 are 2.5V Synchronous
Pipelined SRAMs equipped with QDR architecture. QDR
architecture consists of two separate ports to access the
memory array. The Read port has dedicated Data Outputs to
support Read operations and the Write Port has dedicated
Data Inputs to support Write operations. QDR architecture has
separate data inputs and data outputs to completely eliminate
the need to “turn-around” the data bus required with common
I/O devices. Access to each port is accomplished through a
common address bus. Addresses for Read and Write
addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the device’s Read and Write ports are
completely independent of one another. In order to maximize
data throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with four 18-bit words (CY7C1305BV25) and four
36-bit words (CY7C1307BV25) that burst sequentially into or
out of the device. Since data can be transferred into and out
of the device on every rising edge of both input clocks (K/K and
C/C) memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C131-15NC | CAP 10UF 63V ELECT EB RADIAL |
| CY7C141-15NC | 1K x 8 Dual-Port Static Ram |
| CY7C1312AV18 | 18-Mb QDR-II SRAM 2-Word Burst Architecture(18-Mb QDR-II SRAM（2-Word Burst結(jié)構(gòu)）) |
| CY7C1312BV18 | 18-Mbit QDR-II SRAM 2-Word Burst Architecture(18-Mb QDR-II SRAM（2-Word Burst結(jié)構(gòu)）) |
| CY7C1327F-100AC | 4-Mb (256K x 18) Pipelined Sync SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1305BV25-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 2.5V QDR 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1305BV25-167BZCT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 2.5V QDR 靜態(tài)隨機(jī)存取存儲(chǔ)器 COM RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1305TC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1305TV25-167BZC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 NV靜態(tài)隨機(jī)存取存儲(chǔ)器 167 MHz 2.5V RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1305TV25-167BZXC | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。