參數(shù)資料
型號(hào)： CY7C1312AV18
廠(chǎng)商： Cypress Semiconductor Corp.
英文描述： 18-Mb QDR-II SRAM 2-Word Burst Architecture(18-Mb QDR-II SRAM（2-Word Burst結(jié)構(gòu)）)
中文描述： 18 - MB的QDR - II型SRAM的2字突發(fā)架構(gòu)（18 - MB的QDR - II型的SRAM（2字突發(fā)結(jié)構(gòu)））
文件頁(yè)數(shù)： 1/21頁(yè)
文件大小： 449K
代理商： CY7C1312AV18
PRELIMINARY
18-Mb QDR-II SRAM 2-Word Burst Architecture
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
Cypress Semiconductor Corporation
Document #: 38-05497 Rev. *A
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised June 1, 2004
Features
Separate independent Read and Write data ports
— Supports concurrent transactions
167-MHz clock for high bandwidth
2-Word Burst on all accesses
Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 333 MHz) @ 167MHz
Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
Two output clocks (C and C) account for clock skew
and flight time mismatching
Echo clocks (CQ and CQ) simplify data capture in high
speed systems
Single multiplexed address input bus latches address
inputs for both Read and Write ports
Separate Port Selects for depth expansion
Synchronous internally self-timed writes
Available in x8, x18, and x36 configurations
Full data coherancy , providing most current data
Core Vdd=1.8V(+/-0.1V);I/O Vddq=1.4V to Vdd
13 x 15 x 1.4 mm 1.0-mm pitch FBGA package, 165 ball
(11x15 matrix)
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310AV18 – 2M x 8
CY7C1312AV18 – 1M x 18
CY7C1314AV18 – 512K x 36
Logic Block Diagram (CY7C1310AV18)
Functional Description
The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are
1.8V Synchronous Pipelined SRAMs, equipped with QDR-II
architecture. QDR-II architecture consists of two separate
ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data Inputs to support Write opera-
tions. QDR-II architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus. The
Read address is latched on the rising edge of the K clock and
the Write address is latched on the rising edge of the K clock.
Accesses to the QDR-II Read and Write ports are completely
independent of one another. In order to maximize data
throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with two 8-bit words (CY7C1310AV18) or 18-bit
words (CY7C1312AV18) or 36-bit words (CY7C1314AV18)
that burst sequentially into or out of the device. Since data can
be transferred into and out of the device on every rising edge
of both input clocks (K and K and C and C), memory bandwidth
is maximized while simplifying system design by eliminating
bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
CLK
Gen.
A
(19:0)
K
K
Control
Logic
Address
Register
D
[7:0]
R
Read Data Reg.
RPS
WPS
BWS
[1:0]
Q
[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
8
20
8
16
8
V
REF
W
8
A
(19:0)
20
C
C
8
1
1
Write
Reg
Write
Reg
CQ
CQ
8
DOFF
相關(guān)PDF資料
PDF描述
CY7C1312BV18 18-Mbit QDR-II SRAM 2-Word Burst Architecture(18-Mb QDR-II SRAM（2-Word Burst結(jié)構(gòu)）)
CY7C1327F-100AC 4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F-225AC 4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F-225AI 4-Mb (256K x 18) Pipelined Sync SRAM
CY7C1327F-225BGC 4-Mb (256K x 18) Pipelined Sync SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1312AV18-133BZC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 1.8V 18M-Bit 1M x 18 0.5ns 165-Pin FBGA
CY7C1312BV18-1678ZCES 制造商:Cypress Semiconductor 功能描述:
CY7C1312BV18-167BZC 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 1.8V COM QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1312BV18-167BZCT 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 1.8V COM QDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1312BV18-167BZI 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 1Mx18 1.8V DDR II 靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪(fǎng)問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
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